SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

5.2 OSPI/QSPI Memory Implementation

The OSPI Flash memory interface is the primary bootloader memory location for the AM263P MCU and the QSPI Flash memory interface is the primary bootloader memory location for the AM263x MCU. For a full description of boot ROM execution, including OSPI and QSPI boot information, see the AM263x Sitara™ Microcontroller Technical Reference Manual and AM263Px Sitara™ Microcontroller Technical Reference Manual. The excerpt from Figure 5-4 shows the implementation of the QSPI NOR flash interface from the LP-AM263 LaunchPad design. The excerpt from Figure 5-5 shows the implementation of the OSPI NOR flash interface on the TMDSCNCD263P AM263Px controlCard design.

GUID-20230518-SS0I-MQP4-TJKL-HZVSZGZ6TRTF-low.png Figure 5-4 Example AM263x QSPI Controller and NOR Flash Memory Schematic
GUID-C78E250E-E64A-46ED-BD7B-ACCBE2141811-low.png Figure 5-5 Example AM263Px OSPI Controller and NOR Flash Memory Schematic

To control OSPI/QSPI bus transition overshoot and undershoot, include the following series termination resistors close to the OSPI/QSPI memory pins and the AM263x or AM263Px BGA.

  • Series termination at the AM263x or AM263Px MCU, transmit side of QSPI0_CLK, and QSPI0_CS[1:0]
  • Series termination at OSPI/QSPI memory side of OSPI0_D[7:0] or QSPI0_D[3:0]

For recommended series termination resistor placement, see Figure 5-7.

The OSPI_D[7:1] and QSPI_D[3:1] bits of the interface are used as a read interface, so series termination at the memory side of the bus are used. OSPI/QSPI_D0 may benefit from termination at both the MCU side and the OSPI/QSPI memory side of the bus since is used as both a single-mode write and part of single-mode and octal/quad-mode reads. However, placement of additional termination on both sides of this bus may be difficult to achieve from a PCB floor-planning perspective. The termination scheme presented here should be used as a minimum recommendation. For more details on termination requirements, see Section 8.

Pull resistors are also also necessary on the OSPI/QSPI clock, chip-select and data lines. Include the following pull resistors on the QSPI signals. Different QSPI memory may have different pull-up/down requirements depending on the specific memory and application requirements. These pull resistor recommendations are based on the implementation of the S25FL128x memory used on the LP-AM263 design. To confirm all pin memory configuration details, see the device-specific QSPI Flash memory data sheet.

  • QSPI_CLK, QSPI_CS[1:0], and QSPI_D[1:0] - include 100 kohm pull-up to VDDS33 IO suppply
  • QSPI_D[2] - 10 kohm pull-up to VDDS33 IO supply. This disables write-protect mode on the S25FL128 flash memories.
  • QSPI_D[3] - 10 kohm pull-up to VDDS33 IO supply. This disables hold mode on the S25FL128 flash memories
Include the following pull resistors on the OSPI signals. Different OSPI memory may have different pull-up/down requirements depending on the specific memory and application requirements. These pull resistor recommendations are based on the implementation of the IS25LX256x memory used on the TMDSCNCD263P design. To confirm all pin memory configuration details, see the device specific OSPI Flash memory data sheet.
  • OSPI_CLK - include 100kohm pull-down to GND
  • OSPI_CS - 10kohm pull-up to VDDS33 IO supply
  • OSPI_DQS - 1k pull-down to GND
  • OSPI_D[2] - 4.7kohm pull-up to VDDS33 IO supply. This disables write-protect mode on the IS25LX256 flash memories
  • OSPI_D[1:0] and OSPI_D[7:3] - 49.9kohm pull-up to VDDS33 IO supply

Stronger pull-up resistors are used to disable write-protect and hold modes by default. Weaker pull-up resistors are used to keep the lines at valid logic levels between transactions. Pull resistors should be placed close to the OSPI/QSPI memory pins to prevent any additional routing stubs from being formed.

GUID-20220808-SS0I-TJQW-PNHR-HDF0CGZRZ1QW-low.png Figure 5-6 Excerpt From LP-AM263 Launchpad Layout – Highlighting SOP0/QSPI_D0 Path and SOP Isolation Resistor

Additional routing guidelines for the QSPI memory interface are provided in Figure 5-7 and Table 5-2. These should be used as maximum routing delay and skew match limits. The QSPI memory should be placed close to the AM263x or AM263Px BGA footprint as possible. This allows for routing that maximizes the delay margins and skew margins and minimizes transmission-line effects.

GUID-20230518-SS0I-Q2W8-RKDG-KTDNNBVLLPGN-low.svg Figure 5-7 AM263x or AM263Px QSPI - Routing Rules Diagram

Additional routing guidelines for the OSPI memory interface are provided in Figure 5-8 and Table 5-3. These should be used as maximum routing delay and skew match limits. The OSPI memory should be placed close to the AM263Px BGA footprint as possible. This allows for routing that maximizes the delay margins and skew margins and minimizes transmission-line effects.

GUID-20220404-SS0I-PDB6-GVBL-HZQPFRK76WHF-low.gif Figure 5-8 AM263Px OSPI - Routing Rules Diagram
Table 5-2 AM263x and AM263Px QSPI – Recommended Routing Rules
Spec No. Specification Value Unit
1 QSPI_CLK, QSPI_CS0, QSPI_D[3:0] maximum delay 450 ps
2 QSPI_CLK to QSPI_D[3:0] maximum skew 50 ps
3 Approximate maximum routing distances 3214 mils
4 Approximate maximum routing skew 357 mils
5 A series termination resistor (R1 in diagram above) should be placed close to the QSPI_CLK transmit pin of the AM263x to control rise-time and reflections of the clock line. Variable, 0 to 40 Ω
6 A series termination resistor (R2 in diagram above) should be placed close to the QSPI data pins of the attached memory to control rise-time and reflections of the data lines. Variable, 0 to 40 Ω
Table 5-3 AM263Px OSPI – Recommended Routing Rules
Spec No. Specification Value Unit
1 OSPI_CLK, OSPI_CS0, OSPI_D[7:0] maximum delay 450 ps
2 OSPI_CLK to OSPI_D[7:0] and OSPI_CSn maximum skew 60 ps
3 OSPI_CLK to OSPI_DQS maximum skew 30 ps
4 Approximate maximum routing distances 3214 mils
5 OSPI_CLK to OSPI_D[7:0] and OSPI_CSn approximate maximum routing skew 429 mils
6 OSPI_CLK to OSPI_DQS approximate maximum routing skew 214 mils
7 A series termination resistor (R1 in diagram above) should be placed close to the OSPI_CLK transmit pin of the AM263Px to control rise-time and reflections of the clock line. Variable, 0 to 40 Ω
8 Series termination resistor should be placed close to the OSPI data pins of the attached memory and the AM263Px device to control rise-time and reflections of the data lines. Variable, 0 to 40 Ω
Note: Approximate routing distances are computed assuming a typical 140 ps/inch propagation delay in 50-Ω FR4 Microstrip or Stripline transmission lines. A 2D field solver or appropriate closed-form approximate impedance model should be used to find more exact propagation delay for your specific stackup and routing.