Parity detection identifies single bit errors in a read access. The parity circuitry sets the parity bits when the SRAM word location is written and verifies that there are no single bit errors in the word when it is read back. This is done within the read/write cycles, so no CPU overhead his involved. Should the parity circuitry identify an error, it generates a high priority interrupt to the CPU.

This detection mechanism is simple and relatively inexpensive to implement in semiconductor devices. Parity addresses the Safe State perspective for Safety. As described earlier in Section 2 and Section 4.1 virtually all SRAM failures in-system are likely to be single bit per word failures. This applies to both physical defect mechanisms as well as soft errors. Additional coverage can be provided by also protecting the memory address bits with parity.