SPRACC0A November   2017  – November 2020 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1

 

  1.   Trademarks
  2. 1 Introduction and Scope
  3. 2 SRAM Bit Array
  4. 3 Sources of SRAM Failures
    1. 3.1 Manufacturing Defects
      1. 3.1.1 Time Zero Fails
      2. 3.1.2 Latent Fails
    2. 3.2 Circuit Drift With Usage
    3. 3.3 Circuit Overstress
    4. 3.4 Soft Errors
      1. 3.4.1 Radioactive Events
      2. 3.4.2 Dynamic Voltage Events
      3. 3.4.3 Summary of Error Sources
  5. 4 Methods for Managing Memory Failures in Electronic Systems
    1. 4.1 Start-Up Testing
    2. 4.2 In-System Testing
    3. 4.3 Parity Detection
    4. 4.4 Error Detection and Correction (EDAC)
    5. 4.5 Redundancy
  6. 5 Comparisons and Conclusions
  7. 6  C2000 Memory Types Example
    1. 6.1 TMS320F2837xD
  8. 7 Memory Types
    1. 7.1 Dedicated RAM (Mx and Dx RAM)
    2. 7.2 Local Shared RAM (LSx RAM)
    3. 7.3 Global Shared RAM (GSx RAM)
    4. 7.4 CPU Message RAM (CPU MSGRAM)
    5. 7.5 CLA Message RAM (CLA MSGRAM)
  9. 8 Summary
  10. 9 References
  11. 10Revision History

4.4 Error Detection and Correction (EDAC)

Error detection and correction (often referred to as ECC) goes beyond parity in that it corrects single bit errors. The EDAC circuitry can also detect a 2-bit uncorrectable error. It is possible to implement 2-bit correction, but per the discussions in Section 2 and Section 4.1, this does not provide a good return for the added cost and timing overhead.

EDAC addresses the system availability perspective for safety since the system will continue to run unabated in the presences of a single bit error.

However, EDAC:

  • Adds significant cost to the memory portion of the device
  • Slows down the CPU due to the added SRAM access time necessary to make corrections on the fly
  • Requires more system power

For example consider the following:

  • SRAM on a device is about 1/3 the cost
  • EDAC cost adder to the SRAM is 30%
  • EDAC requires the addition of a wait state to the memory access time
  • The price of the device goes up ~40%

Not all the SRAM necessarily requires EDAC protection so this can vary with device designs. Likewise there are ways to reduce access time to less than a wait state.