SPRACI7A October 2018 – March 2022 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SJ-Q1
Memory power on self test can be enabled by configuring the “Z1-OTP-BOOT-GPREG2” register as given in Table 5-1. All the requirements as mentioned in the ROM Code and Peripheral Booting section of the TRM needs to be adhered to for configuring these USER OTP bits.
Bit | Name | Description | Boot ROM Action |
---|---|---|---|
31-24 | Key | Write 0x5A to these 8-bits to tell the boot ROM code that the bits in this register are valid | If set to 0x5A, boot ROM uses the values in this register. If set to any other value, boot ROM ignores the values in this register. |
23-8 | Reserved | Reserved | No action |
7-6 | Reserved | Configures the memory power on self-test | |
0x0 - Execute self-test | |||
0x1 - No action (Reserved) | |||
0x2 - No action (Reserved) | |||
0x3 - No action (Reserved) | |||
5-4 | Error Status Pin | Sets the GPIO pin to be used as the ERRORSTS | No action |
0x0 – GPIO24 | |||
0x1 – GPIO28 | |||
0x2 – GPIO29 | |||
0x3 – ERRORSTS disabled (Default) | Boot ROM configures the appropriate mux for the selected GPIO pin | ||
3-0 | Reserved | Reserved | No action |