SPRACI7A October   2018  – March 2022 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Overview of Memory Test Requirements
    2. 1.2 Terms and Definitions
  3. 2System Challenges to Memory Validation
    1. 2.1 Memory Test Flow
    2. 2.2 SRAM test Algorithmic Coverage
    3. 2.3 ROM Test Algorithmic Coverage
  4. 3Summary
  5. 4References
  6.   A M-POST Working in F28004x
    1.     A.1 Enabling of Test
    2.     A.2 M-POST Duration
    3.     A.3 M-POST Result
    4.     A.4 Periodic Self-Test
  7.   Revision History

2.2 SRAM test Algorithmic Coverage

Device SRAMs are tested using March13n algorithm. This algorithm ensures that:

  • The bit cell can be written and read as both a 1 and a 0
  • Bridging defects between adjacent bit cells are detected
  • The row and column decode is such that the targeted bits (and only the targeted bits) are affected on a write
  • The row and column decode is such that only the targeted bits are presented to the boundary of the memory on a specified read

The sequence of operations included during the test of an SRAM is given in .

Table 2-1 March13n Test Sequence
AddressInitializationMarch Element 1March Element 2March Element 3March Element 4
0Wr(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)
1Wr(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)//
2Wr(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)
|\\\Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)
N-1Wr(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)Rd(0), Wr(1), Rd(1)Rd(1), Wr(0), Rd(0)