SPRACI7A October 2018 – March 2022 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SJ-Q1
M-POST is enabled with the help of a Programmable Built in Self-Test (PBIST) solution, which is used for the manufacturing test of the device. PBIST has a CPU configurable interface used for field self-test in addition to the Automated Test Equipment (ATE) interface used during manufacturing test.
The PBIST architecture consists of a controller which is specifically designed toward efficient memory testing. The controller is designed with a dedicated register set and a highly specialized pipeline and instruction set targeted specifically toward testing memories. Furthermore, the PBIST engine is equipped with multiple read and multiple write memory ports, or buses, which enable it to efficiently test multiple memory instances in parallel. The PBIST controller also has access to the PBIST ROM. The PBIST ROM is where test routines are stored for the PBIST engine to fetch and execute. These test routines are fetched by the PBIST controller and executed on multiple on-chip memory instances in parallel. Because of the specialized architecture and test routines, PBIST provides very high diagnostic coverage on the implemented SRAMs and ROMs at a transistor level in a very efficient manner. Because PBIST controller has direct access to the ROMs and SRAMs, it is even able to test secure memory instances on devices equipped with DCSM (Dual Zone Code Security Module). For details on leveraging the DCSM on F28004x, see Achieving Coexistence of Safety Functions for EV/HEV Using C2000™ MCUs.
The steps involved in the execution of memory self-test are described in Figure 2-2.