SPRACM3E August 2021 – January 2023 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The node devices receive the ping packet and they have to generate the EPWM sync signals after a certain delay depending on the order of device in the node. The delay configuration is done in the fsi_daisy_epwmsync_node.syscfg file provided along with the project. The configuration has to be done using the counter value ‘match’ in the Configurable Logic Block (CLB) under the Counter0 tab as shown in Figure 7-6. FSM block contains the logic to generate the EPWM sync-in signal after the match count delay once it gets the ping packet received signal. The CLB configuration done using the sysconfig file can be seen in the clb.html file under the syscfg tab in the project when the project is built using the CPU1_CLB build configuration as is shown in Figure 7-7.
Similar to the lead device, the user can configure the EPWM frequency and duty cycle for the respective node using EPWM_TIMER_TBPRD for frequency, EPWM_CMPA_VALUE for EPWM1A duty cycle and EPWM_CMPB_VALUE for EPWM1B duty cycle.
The CLB configuration differs slightly from F28004x to F28002x. F28004x devices have to route CLBx_OUT to FSITX external trigger connection through the EPWM XBAR while the F28002x devices have been updated to directly connect FSITX external connection to CLBx_OUT. User can refer to the device reference manual which explains the specific information.