SPRACM3E August   2021  – January 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Using the Fast Serial Interface (FSI) With Multiple Devices in an Application
  2.   Trademarks
  3. 1Introduction to the FSI Module
  4. 2FSI Applications
  5. 3Handshake Mechanism
    1. 3.1 Daisy-Chain Handshake Mechanism
    2. 3.2 Star Handshake Mechanism
  6. 4Sending and Receiving FSI Data Frames
    1. 4.1 FSI Data Frame Configuration APIs
    2. 4.2 Start Transmitting Data Frames
  7. 5Daisy-Chain Topology Tests
    1. 5.1 Two Device FSI Communication
      1. 5.1.1 CPU Control
      2. 5.1.2 DMA Control
      3. 5.1.3 Hardware Control
    2. 5.2 Three Device FSI Communication
      1. 5.2.1 CPU/DMA Control
      2. 5.2.2 Hardware Control
        1. 5.2.2.1 Skew Compensation for Three Device Daisy-Chain System
          1. 5.2.2.1.1 CPU/DMA control
          2. 5.2.2.1.2 Hardware Control
  8. 6Star Topology Tests
  9. 7Event Synchronization Over FSI
    1. 7.1 Introduction
      1. 7.1.1 Requirement of Event Sync for Distributed Systems
      2. 7.1.2 Solution Using FSI Event Sync Mechanism
      3. 7.1.3 Functional Overview of FSI Event Sync Mechanism
    2. 7.2 C2000Ware FSI EPWM Sync Examples
      1. 7.2.1 Location of the C2000Ware Example Project
      2. 7.2.2 Summary of Software Configurations
        1. 7.2.2.1 Lead Device Configuration
        2. 7.2.2.2 Node Device Configuration
      3. 7.2.3 1 Lead and 2 Node F28002x Device Daisy-Chain Tests
        1. 7.2.3.1 Hardware Setup and Configurations
        2. 7.2.3.2 Experimental Results
      4. 7.2.4 1 Lead and 8 Node F28002x Device Daisy-Chain Tests
        1. 7.2.4.1 Hardware Setup and Configurations
        2. 7.2.4.2 Experimental Results
      5. 7.2.5 Theoretical C2000 Uncertainties
    3. 7.3 Additional Tips and Usage of FSI Event Sync
      1. 7.3.1 Running the Example
      2. 7.3.2 Target Configuration File
      3. 7.3.3 Usage of Event Sync for Star Configuration
  10. 8References
  11. 9Revision History

5.2.1 CPU/DMA Control

  • Test condition

    Device 1 sends data -> Device 2 receives data -> Device 2 moves RX data to TX buffer and sends data to Device 3->…..-> Device 3 moves RX data to TX buffer and sends data to Device 1 -> Device1 receives data and verifies the data matches the originally sent TX data.

  • Test case

    Data length of 8 words, 1 data line, TXCLK = 50 MHz, with setting ① for CPU control case and ② for DMA control case (Table 5-1) enabled.

In the tests, GPIOs are toggled within software when specific events occur during the communication and measured using an oscilloscope to obtain the respective timing data. In the figures below, the green signal represents the GPIO toggling of Device 1 (Lead device), the blue signal represents the GPIO toggling of Device 2 (Node device), and the magenta signal represents the GPIO toggling of Device 3 (Node device).

GUID-9F3B5077-A0F8-43A3-A02A-88B4934F429B-low.png Figure 5-7 FSI Communication With CPU Control Among Three Devices
GUID-EE227CDD-05C2-4883-AFCD-D054A639A944-low.png Figure 5-8 Time of Data Going Through One Device - CPU Control

For the CPU control case, the time needed for the data transmission to complete the three device daisy-chain loop is 16.2 µs, as shown in Figure 5-7. This time will increase by 7.1 us for each device added to the daisy-chain connection system, as shown in Figure 5-8. The 7.1 µs increased time per device includes the time for transmission and moving RX data to the TX buffer and registers.

GUID-8319C212-034E-486E-95D8-8049FE946758-low.png Figure 5-9 FSI Communication With DMA Control Among Three Devices
GUID-3AFFBFAB-2021-40EC-B5D1-39338489D8D8-low.png Figure 5-10 Time of Data Going Through One Device - DMA Control

For the DMA control case, the time needed for the data transmission to complete the three device daisy-chain loop is 6.5 µs, as shown in Figure 5-9. This time will increase by 2.3 us for each device added to the daisy-chain connection system, as shown in Figure 5-10. The 2.3 µs increased time per device includes the time for transmission and moving RX data to the TX buffer and registers.