SPRACN9F May   2023  – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Supporting Documentation
    2. 1.2 Board Designs Supported
    3. 1.3 General Board Layout Guidelines
    4. 1.4 PCB Stack-Up
    5. 1.5 Bypass Capacitors
      1. 1.5.1 Bulk Bypass Capacitors
      2. 1.5.2 High-Speed Bypass Capacitors
    6. 1.6 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK, CMD_ADDR, and CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK, CMD_ADDR, and CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

1.4 PCB Stack-Up

The typical stack-up for routing the DDR interface is a ten layers. However, this can only be accomplished on a board with routing room with large keep-out areas. Additional layers are required if:

  • The PCB layout area for the DDR Interface is restricted, which limits the area available to spread out the signals to minimize crosstalk.
  • Other circuitry must exist in the same area, but on layers isolated from the DDR routing.
  • Additional planes layers are needed to enhance the power supply routing or to improve EMI shielding.

Board designs that are relatively dense may require more layers to properly allow the DDR routing to be implemented such that all rules are met.

All DDR signals must be routed adjacent to a solid VSS reference plane. When multiple VSS reference planes exist in the DDR routing area, stitching vias must be implemented nearby wherever vias transfer signals to a different VSS reference plane. This is required to maintain a low-inductance return current path.

It is strongly recommended all DDR signals be routed as strip-line. Some PCB stack-ups implement signal routing on 2 adjacent layers. This is not recommended as crosstalk occurs on any trace routed parallel to another trace on an adjacent layer, even for a very short distance. It is recommended to route LPDDR4 signals on PCB layers closer to the SoC within the stackup, giving the signal a shorter travel time through the via. The PCB layers farther from the SoC will have longer travel times through the via, which can increase coupling between vias. Both signal and via coupling can lead to smaller timing margins.

Note a shorter via travel could mean a longer via stub (if using standard drill vias), so that is to be considered as well. Simulation can be used to determine if via stub length is an issue.

PCB material is another important factor. Depending on the design specifics, it may be required to use a higher frequency material such as ISOLA I-Speed or equivalent/better to achieve highest data rates (4266 Mbps). Standard FR4 products like 370HR can be used for lower data rates. In specific cases, it is sufficient for higher data rates as well.

Table 1-1 PCB Stack-up Specifications
NumberParameter(6)MINTYPMAXUNIT
PS1PCB routing plus plane layers10
PS2Signal routing layers6
PS3Full VSS reference layers under DDR routing region (1)1
PS4Full VDDS_DDR power reference layers under the DDR routing region (1)1
PS5Number of reference plane cuts allowed within DDR routing region (2)0
PS6Number of layers between DDR routing layer and reference plane (3)0
PS7PCB routing feature size (ie. Copper traces, pads, conductive planes, etc)4Mils
PS8PCB trace width, w4Mils
PS9Point-to-Point, single-ended impedance40Ω
PS10Point-to-Point, differential impedance80Ω
PS11T-Branch, single-ended impedance (5)35/70Ω
PS12T-branch, differential impedance (5)70/140Ω
PS13Impedance control (4)Z-10%ZZ+10%Ω
(1) Ground reference layers are preferred over power reference layers. Return signal vias need to be near layer transitions.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts create large return current paths, which can lead to excessive crosstalk and EMI radiation. Beware of reference plane voids caused by via antipads, as these also cause discontinuities in the return current path.
(3) Reference planes are to be directly adjacent to the signal layer, to minimize the size of the return current loop.
(4) Z is the nominal singled-ended or differential impedance selected for the PCB specified by PS9-PS12.
(5) Balanced T traces (also referred to as T-branch traces) are split traces from source to multiple end points. The target impedance of the split trace should be 2 times the non-branched impedance. See routing topologies. The maximum trace impedance is typically limited by the minimum achievable trace width. Reduction of the non-branched impedance may be necessary to maintain the 2:1 trace impedance ratio.
(6) These specifications are to be used as a starting point for designs. It is recommended each design be extracted and simulated to ensure all requirements are met.