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TDA4AH-Q1

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Automotive analytics SoC for sensor fusion, L2, L3 domain controllers with AI and video encoder

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TDA4AH-Q1

ACTIVE
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Product details

Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 6 Arm Corex-R5F (lockstep opt) CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 depth and motion accelerator, 2 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Security Cryptography, Debug security, Isolation firewalls, Memory protection, Secure boot, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 6 Arm Corex-R5F (lockstep opt) CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 depth and motion accelerator, 2 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Security Cryptography, Debug security, Isolation firewalls, Memory protection, Secure boot, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L RX plus Two CSI2.0 4L TX

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L RX plus Two CSI2.0 4L TX

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.
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Technical documentation

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Type Title Date
* Data sheet TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors datasheet (Rev. B) PDF | HTML 15 Dec 2023
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. B) PDF | HTML 24 Jul 2024
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 Aug 2024
User guide J784S4 J742S2 Technical Reference Manual (Rev. D) 24 Jul 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 Jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 Jun 2024
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14 May 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 Apr 2024
User guide SK-AM69 Processor Start Kit User's Guide (Rev. A) PDF | HTML 18 Mar 2024
Technical article Building multicamera vision perception systems for ADAS domain controllers with integrated processors PDF | HTML 05 Jan 2024
Technical article How to deliver current beyond 100 A to an ADAS processor PDF | HTML 04 Jan 2024
Functional safety information J721E, J721S2, J7200, J784S4 MCAL TUV Certification 22 Dec 2023
User guide J784S4, TDA4VH, TDA4AH, TDA4VP, TDA4AP, AM69 Power Estimation Tool User’s Guide PDF | HTML 07 Dec 2023
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 Nov 2023
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. C) 11 Sep 2023
White paper 以高度整合處理器設計高效邊緣 AI 系統 (Rev. A) PDF | HTML 19 Apr 2023
White paper 고도로 통합된 프로세서를 사용해 효 율적인 에지 AI 시스템 설계 (Rev. A) PDF | HTML 19 Apr 2023
White paper Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13 Mar 2023
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 01 Mar 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 Jan 2023
User guide Jacinto Processors TDA4AP/TDA4VP/TDA4AH/TDA4VH EVM Users Guide PDF | HTML 02 Dec 2022
Functional safety information Jacinto™ 7 Safety Product Overview PDF | HTML 15 Aug 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 Apr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 Apr 2022
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 29 Mar 2022
Technical article How to simplify your embedded edge AI application development PDF | HTML 28 Jan 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 Jan 2022
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 Oct 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 Jul 2021
White paper Jacinto™ 7 프로세서의 보안 구현 도구 04 Jan 2021
White paper Security Enablers on Jacinto™ 7 Processors 04 Jan 2021
White paper Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren 04 Jan 2021
White paper Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™ 22 Oct 2020
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22 Oct 2020
White paper Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원 22 Oct 2020
Application note OSPI Tuning Procedure PDF | HTML 08 Jul 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

J721EXENETXPANEVM — TDA4xP-Q1 & TDA4xH-Q1 evaluation module for Jacinto™ 7 SoCs with quad Ethernet expansion

The J721EXENETXPANEVM expands the capabilities of an evaluation module (EVM) with a quad Ethernet expansion card for evaluating Jacinto™ 7 system-on-a-chip (SoCs) in networking applications for both automotive and industrial markets. The quad-port Ethernet EVM is compatible J784S4XEVM and (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

J784S4XEVM — TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 evaluation module for SoC far-field analytic systems

The J784S4 evaluation module (EVM) is a platform for evaluating the TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 processors in vision analytics and networking applications throughout automotive and industrial markets. These processors perform particularly well in multicamera, sensor fusion and (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

J7EXPCXEVM — Gateway/Ethernet switch expansion card

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

J7EXPEXEVM — Audio and display expansion card

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our audio and display expansion card.
User guide: PDF | HTML
Not available on TI.com
Debug probe

TMDSEMU110-U — XDS110 JTAG Debug Probe

The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all (...)

User guide: PDF
Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Software development kit (SDK)

PROCESSOR-SDK-LINUX-J784S4 — Linux® SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4AP-Q1 — Automotive analytics SoC for L2, L3 domain controllers with Arm® Cortex®-A72, AI and video encoder TDA4VP-Q1 — Automotive SoC for L2, L3 domain controllers with Arm® Cortex®-A72, graphics, AI, video coprocessor TDA4AH-Q1 — Automotive analytics SoC for sensor fusion, L2, L3 domain controllers with AI and video encoder TDA4VH-Q1 — Automotive SoC for sensor fusion, L2, L3 domain controllers with graphics, AI and video coprocessor
Hardware development
Evaluation board
J784S4XEVM — TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 evaluation module for SoC far-field analytic systems
Download options
Software development kit (SDK)

PROCESSOR-SDK-QNX-J784S4 — QNX SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4AP-Q1 — Automotive analytics SoC for L2, L3 domain controllers with Arm® Cortex®-A72, AI and video encoder TDA4VP-Q1 — Automotive SoC for L2, L3 domain controllers with Arm® Cortex®-A72, graphics, AI, video coprocessor TDA4AH-Q1 — Automotive analytics SoC for sensor fusion, L2, L3 domain controllers with AI and video encoder TDA4VH-Q1 — Automotive SoC for sensor fusion, L2, L3 domain controllers with graphics, AI and video coprocessor
Hardware development
Evaluation board
J784S4XEVM — TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 evaluation module for SoC far-field analytic systems
Download options
Software development kit (SDK)

PROCESSOR-SDK-RTOS-J784S4 — RTOS SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4AH-Q1 — Automotive analytics SoC for sensor fusion, L2, L3 domain controllers with AI and video encoder TDA4VH-Q1 — Automotive SoC for sensor fusion, L2, L3 domain controllers with graphics, AI and video coprocessor TDA4AP-Q1 — Automotive analytics SoC for L2, L3 domain controllers with Arm® Cortex®-A72, AI and video encoder TDA4VP-Q1 — Automotive SoC for L2, L3 domain controllers with Arm® Cortex®-A72, graphics, AI, video coprocessor
Hardware development
Evaluation board
J784S4XEVM — TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 evaluation module for SoC far-field analytic systems
Download options
IDE, configuration, compiler or debugger

C7000-CGT — C7000 code generation tools - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)
View Options
IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.
Launch Download options
IDE, configuration, compiler or debugger

DDR-CONFIG-J784S4 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4AP-Q1 — Automotive analytics SoC for L2, L3 domain controllers with Arm® Cortex®-A72, AI and video encoder TDA4VP-Q1 — Automotive SoC for L2, L3 domain controllers with Arm® Cortex®-A72, graphics, AI, video coprocessor TDA4AH-Q1 — Automotive analytics SoC for sensor fusion, L2, L3 domain controllers with AI and video encoder TDA4VH-Q1 — Automotive SoC for sensor fusion, L2, L3 domain controllers with graphics, AI and video coprocessor AM69 — General purpose octal core 64-bit Arm Cortex-A72 with graphics, PCIe Gen 3, Ethernet, USB 3.0 AM69A — 32 TOPS vision SoC for 1-12 cameras, autonomous mobile robots, machine vision, mobile DVR, AI-BOX
Hardware development
Evaluation board
SK-AM69 — AM69 and AM69A starter kit for vision AI and general purpose processors
Launch
IDE, configuration, compiler or debugger

SAFETI_CQKIT — Safety compiler qualification kit

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
View Options
IDE, configuration, compiler or debugger

SYSCONFIG — System configuration tool

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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Operating system (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino® real-time operating system (RTOS)

The QNX Neutrino® Realtime Operating System (RTOS) is a full-featured and robust RTOS designed to enable the next-generation of products for automotive, medical, transportation, military and industrial embedded systems. Microkernel design and modular architecture enable customers to create (...)
From: QNX Software Systems
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Simulation model

AM69 TDA4VH TDA4AH TDA4VP TDA4AP Thermal Model (Rev. A)

SPRM843A.ZIP (0 KB) - Thermal Model
Download
Simulation model

AM69A,TDA4VH-Q1,TDA4AH-Q1,TDA4VP-Q1,TDA4AP-Q1 BSDL MODEL

SPRM840.ZIP (18 KB) - BSDL Model
Download
Simulation model

IBIS Model for AM69 TDA4VH TDA4AH TDA4VP TDA4AP

SPRM836.ZIP (1497 KB) - IBIS Model
Download
Package Pins CAD symbols, footprints & 3D models
FCBGA (ALY) 1414 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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