SPRACN9F May   2023  – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

1.   1
2.   Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines
3.   Trademarks
4. 1Overview
   1. 1.1 Supporting Documentation
   2. 1.2 Board Designs Supported
   3. 1.3 General Board Layout Guidelines
   4. 1.4 PCB Stack-Up
   5. 1.5 Bypass Capacitors
      1. 1.5.1 Bulk Bypass Capacitors
      2. 1.5.2 High-Speed Bypass Capacitors
   6. 1.6 Velocity Compensation
5. 2LPDDR4 Board Design and Layout Guidance
   1. 2.1  LPDDR4 Introduction
   2. 2.2  LPDDR4 Device Implementations Supported
   3. 2.3  LPDDR4 Interface Schematics
   4. 2.4  Compatible JEDEC LPDDR4 Devices
   5. 2.5  Placement
   6. 2.6  LPDDR4 Keepout Region
   7. 2.7  Net Classes
   8. 2.8  LPDDR4 Signal Termination
   9. 2.9  LPDDR4 VREF Routing
   10. 2.10 LPDDR4 VTT
   11. 2.11 CK, CMD_ADDR, and CTRL Topologies
   12. 2.12 Data Group Topologies
   13. 2.13 CK, CMD_ADDR, and CTRL Routing Specification
   14. 2.14 Data Group Routing Specification
   15. 2.15 Channel, Byte, and Bit Swapping
6. 3LPDDR4 Board Design Simulations
   1. 3.1 Board Model Extraction
   2. 3.2 Board-Model Validation
   3. 3.3 S-Parameter Inspection
   4. 3.4 Time Domain Reflectometry (TDR) Analysis
   5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
         1. 3.5.3.1 Waveform Quality
         2. 3.5.3.2 Eye Quality
         3. 3.5.3.3 Delay Report
         4. 3.5.3.4 Mask Report
   6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
7. 4Revision History

Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines