SPRACN9F May   2023  – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Supporting Documentation
    2. 1.2 Board Designs Supported
    3. 1.3 General Board Layout Guidelines
    4. 1.4 PCB Stack-Up
    5. 1.5 Bypass Capacitors
      1. 1.5.1 Bulk Bypass Capacitors
      2. 1.5.2 High-Speed Bypass Capacitors
    6. 1.6 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK, CMD_ADDR, and CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK, CMD_ADDR, and CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

2.13 CK, CMD_ADDR, and CTRL Routing Specification

Skew within the CK, CMD_ADDR, and CTRL net classes can reduce setup and hold margin for the signals at the SDRAM device. Thus, this skew must be controlled. The routed PCB track has a delay proportional to its length. Thus, the delay skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match skew on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. Make sure to include the Z-axis delays (vias) during analysis.

Table 2-6 lists the limits for the individual segments that comprise the routing from the processor to the SDRAM. These segment lengths coincide with the CK, CMD_ADDR, and CTRL topology diagrams shown previously in Table 2-6, Figure 2-7, and Figure 2-8. By controlling the routed lengths for the same segments of all signals in a routing group, the signal delay skews are controlled. Most PCB layout tools can be configured to generate reports to assist with this validation. If this cannot be generated automatically, this must be generated and verified manually.

These parameters are recommendations only, intended to get the design close to success prior to simulation. To ensure the PCB design meets all requirements, it is required the design be simulated and those results compared with the simulation results defined in Section 3.

Table 2-6 CK, CMD_ADDR, and CTRL Routing Specifications
NumberParameterMINTYPMAXUNIT
LP4_ACRS1Propagation delay of net class CK
RSAC1 + RSAC2		300 (1)ps
LP4_ACRS2Propagation delay of net class CMD_ADDR and CTRL
RSAC3 + RSAC4, RSAC5		300 (1)ps
LP4_ACRS3Skew within net class CK (CK+ to CK- Skew)
(RSAC1 + RSAC2) Skew

(9)

0.75 (2)ps
LP4_ACRS4aSkew across net class CMD_CTRL
RSAC3 + RSAC4 Skew (9)

10

30

ps

LP4_ACRS4b

Skew across net class CTRL
RSAC3 + RSAC4, RSAC5 Skew (9)

10

30

ps
LP4_ACRS5Skew between each T-branch signal pair
RSAC2 or RSAC4 Skew (7)		0.1ps
LP4_ACRS6Skew across CMD_ADDR, and CTRL and associated CK clock net class
RSAC1+ RSAC2, RSAC3 + RSAC4, RSAC5 (9)

60

ps
LP4_ACRS7Vias per trace4vias
LP4_ACRS8Via Stub Length (8)20Mils
LP4_ACRS9Via count difference0 (3)vias
LP4_ACRS10Center-to-center CK to other LPDDR4 trace spacing4w (4)
LP4_ACRS11Center-to-center CMD_ADDR, CTRL to other LPDDR4 trace spacing3w (4)
LP4_ACRS12Center-to-center CMD_ADDR, CTRL to self or other CMD_ADDR, CTRL trace spacing3w (4)
LP4_ACRS13CK center-to-center spacing (5), (6)
LP4_ACRS14CK spacing to other non-DDR net4w (4)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) To be verified by design/simulation, confirming JEDEC defined Vix_CK_ratio (25%) are satisfied with good eye margins.
(3) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
(4) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints). Spacing minimums may be relaxed if simulations accurately capture crosstalk between neighboring victim and aggressor traces show good margin. Also consider via spacing. Signals with adjacent vias near SoC should NOT have adjacent vias near DRAM.
(5) CK spacing set to ensure proper differential impedance.
(6) The user must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.
(7) Skew control on branch trace segments (Balance T) is intended to optimize signal integrity (waveform reflections). It is not required nor recommended to match skew across all branch trace segments, just for each branch of a specific signal.
(8) Via stub length control (micro-via or backdrill) may be required if operating LPDDR4 above 3200 Mbps (depending on simulation).
(9) Recommend routing net classes CK, CMD_ADDR, and CTRL on same signal layer for better skew control.
(1)

Consider the delays from SoC die pad to the DRAM pin (ie. Delays include SoC package plus PCB). Consider only one leg of any T-branch trace segments.