SPRACN9F May   2023  – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Supporting Documentation
    2. 1.2 Board Designs Supported
    3. 1.3 General Board Layout Guidelines
    4. 1.4 PCB Stack-Up
    5. 1.5 Bypass Capacitors
      1. 1.5.1 Bulk Bypass Capacitors
      2. 1.5.2 High-Speed Bypass Capacitors
    6. 1.6 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK, CMD_ADDR, and CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK, CMD_ADDR, and CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

3.6.1 Stack-Up

These guidelines recommend a 10 layer PCB stack-up for full device entitlement. Below is an example stack-up from a 10Lyr reference design.

  • Designs using FR4 products like 370HR are supported, but also recommend higher speed materials like ISOLA I-Speed (or equivalent) for increased margin.
  • This example routes data groups on layers 2 and 4. While this minimizes the via travel and therefore reduces via-to-via coupling, but it leaves a longer via stub, which might require back-drill.
  • Dynamic CA signals are routed on layer 7, and more static control signals routed on layer 9.
Table 3-4 Example PCB Stackup for LPDDR4
Layer No Stackup Routing Plan Highest Priorities and Layer
Solder mask
1 TOP - PWR/SIG BGA breakouts/VDD_CPU, VDD_CORE and VDD_DDR_1V1
2 PWR/SIG VDD_CPU and CORE/LPDDR (DBG #3/#1, CAT-Branches)
3 GND REF
4 PWR/SIG VDDA_PHYCORE_0V8, VDD_xxx, 0V85/LPDDR (DBG #2/#0)
5 PWR/GND VDDA_0V8_xxx and GND flood for LPDDR4
6 PWR/GND VDD_xxx, VDDA_xxx supplies and GND flooded for LPDDR4
7 SIG/PWR VDD_xxx, VDDA_xxx/LPDDR (Dynamic CA, Trunks)/SERDES
8 GND REF
9 SIG/PWR VDD_xxx, VDDA_xxx/LPDDR (static CA)
10 BOTTOM - SIG/PWR BGA breakouts/Pwr and GND plan segments
Solder mask

Table 3-5 provides simulation results performed on sample designs, showing the impact of the PCB stackup (material, drill plan, and so forth) on LPDDR4 performance. The results showed that maximum bandwidth could be achieved on a FR4 solution, but required back-drilling. The higher frequency material could achieve same performance without back drill. Note the 8 layer design only achieved 3733, but this was due to other design compromises due to limited layers (solid reference planes, and so forth).

Table 3-5 LPDDR4 Performance Impact From StackUp
Design Material Layer Count Via Back Drilling Maximum LPDDR4 Speed (Mbps)
EVM I-Speed 16 Yes 4266
Ref Board I-Speed 10 No 4266
Ref Board 370HR 10 Yes 4266
Ref Board 370HR 8 No 3733