SPRACN9F May 2023 – August 2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1
Skew within the Byte signal net class directly reduces the setup and hold margin for the DQ and DM nets. As described with the ADDR_CTRL signal net class and associated CK clock net class, this skew must be controlled. The data byte skew must be managed through controlling the lengths of the routed tracks within a defined group of signals. The only way to practically match skews on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. Make sure to include the Z-axis delays (vias) during analysis.
Table 2-7 contains the routing specifications for the Byte0, Byte1, Byte2, and Byte3 routing groups. Each signal net class and its associated clock net class is routed and matched independently. These parameters are recommendations only, intended to get the design close to success prior to simulation. To ensure the PCB design meets all requirements, it is required the design be simulated and those results compared with the simulation results defined in Section 3.
Number | Parameter | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
LP4_DRS1 | Propagation delay of net class DQSx RSD1 (4) |
300 (2) | ps | ||
LP4_DRS2 | Propagation delay of net class BYTEx RSD2 |
300 (2) | ps | ||
LP4_DRS3 | Propagation delay of each DQS pair must be less than propagation delay of CK pair. RSD1 < (RSAC1 + RSAC2) (4) | 0 | ps | ||
LP4_DRS4 | Skew within net class DQSx RSD1 Skew (DQS+ to DQS-) (4)(5) |
0.75 | ps | ||
LP4_DRS5 | Skew across net class DQSx and BYTEx RSD1 to RSD2 Skew (1), (4), (5) |
5 |
25 |
ps | |
LP4_DRS6 | Propagation delay of each DQS pair must be less than propagation delay DQ/DM. RSD1 < RSD2 (4) | 0 | 150 ps | ps | |
LP4_DRS7 | Vias Per Trace | 2 (2) | vias | ||
LP4_DRS8 | Via Stub Length (3) | 40 | Mils | ||
LP4_DRS9 | Via Count Difference | 0 (6) | vias | ||
LP4_DRS10 | RSD1 center-to-center spacing (between clock net class) (7) | 4w | |||
LP4_DRS11 | RSD1 center-to-center spacing (within clock net class) (8), (9) | ||||
LP4_DRS12 | RSD2 center-to-center spacing (between signal net class) (7) | 4w | |||
LP4_DRS13 | RSD2 center-to-center spacing (within signal net class)(7) | 3w |