In order to achieve the high frequency targets for Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 interfaces, an optimal PCB implementation is required. TI highly recommends that customer design copies the LPDDR4 PCB of the specific device EVM exactly, and in every detail (PCB material, routing, spacing, vias w/ back-drill, and so forth) in order to achieve the full specified interface frequency/data rate. If the design does not or cannot copy the TI solution, TI's EVM should still be used as a starting point/reference. Based on any compromises made, the customer design may need to constrain the interface frequency/data rate.

The goal of this document is to define a set of layout, routing, and simulation rules that allow designers to successfully implement a robust design for the topologies that TI supports. It is also required that the PCB design be simulated to ensure the design targets are achieved. TI will limit debug/support for boards that have not been designed and simulated according to the steps defined in this document. Systems that do not follow the TI EVM implementations and/or do not have valid simulation results will likely need to run at a reduced DDR frequency.

This document provides Reference eye masks as guidance for validation of the simulations results. It is still expected that the PCB design work (design, layout, and fabrication) is performed and reviewed by a highly knowledgeable high-speed PCB designer. Problems such as impedance discontinuities when signals cross a split in a reference plane can be detected visually by those with the proper experience.

TI only supports board designs that follow the guidelines in this document. These guidelines are based on well-known transmission line properties for copper traces routed over a solid reference plane. Declaring insufficient PCB space does not allow routing guidelines to be discounted. TI will limit debug/support for designs that have not been simulated according to the steps defined in this document.