The controller implemented for the open loop and closed loop plots shown in Figure 38 and Figure 39 is a dead beat controller where the output catches up to the input in just one sample cycle without any overshoots or requiring multiple cycles. From the closed loop plot, it is clear that the closed loop gain is always 0dB (unity gain) at all frequencies and, therefore, magnitude-based bandwidth determination is not practical. Hence, the phase plot is chosen as reference and the frequency at which the phase lag goes beyond 90° is taken as bandwidth per the NEMA ICS 16 (speed loop). In this test case, the PWM frequency is chosen as 10 KHz and the sampling frequency is 20 KHz and the current loop bandwidth obtained from the closed loop plot is about 5000Hz per these guidelines.
Phase margin determination from open loop plot.
From the open loop plots, the phase margin obtained is about 65°. Such a high margin should give a very robust performance across the frequency ranges within the bandwidth obtained.
Maximum modulation index determination from PWM update time.
From Section 7.3.1, the time lapse between feedback sampling instantiation to PWM update is about 1.75 µs. In this system where the PWM frequency is 10 KHz, the maximum modulation index is limited by the sampling method as follows:
Double sampling - just above 96% (F2837x), or 93% (F28004x)
Single sampling - just about 98% (F2837x), or 96% (F28004x)
This is quite comparable to FPGA based systems where the entire algorithm is implemented in hardware.
Voltage decoupling in current loop
The SFRA test can be performed at zero speed (by rigidly locking the shaft if needed) to get one plot as reference. The gain crossover frequency and phase margin at zero speed may be noted down. Then at different speeds and load conditions, this test can be repeated to verify if there is any change in bandwidth or phase margin. Any variation in the plot at different speed is indicative of the quality of decoupling in current loops.