SPRACT2 August 2020 – MONTH AM67 , AM67 , AM67A , AM67A , AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VP-Q1
The OSPI tuning algorithm tunes the PHY by identifying the key features of the passing region. These key features are:
In order to test whether a TX/RX/Read Delay combination passes, the tuning algorithm configures the PHY to that setting, and reads a known pattern from the OSPI memory. The test pattern can be found in the associated zip file: . The tuning algorithm searches along the line between points (1) and (2), testing TX/RX combinations between them, and identifies the position of the boundary represented by line (3). The algorithm then identifies which ref_clk target is associated with the largest passing region, and sets TX/RX delays into the corresponding corner, leaving some margin for the TX/RX minimum and maximum to shift. Figure 2-4 shows the placement of the OTP in two scenarios, based on which passing region is larger.
If only one tuning window is detected, the OTP is placed according to temperature, as shown in Figure 2-5.
For implementation details of the algorithm, see . Information on tuning the PHY in SDR mode will be included in later versions of this document. Considerations for using this algorithm at frequencies other than 166 MHz will also be addressed.