SPRACU1A October   2020  – June 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  3. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  VPP
    8. 2.8  Net Classes
    9. 2.9  DDR4 Signal Termination
    10. 2.10 VREF Routing
    11. 2.11 VTT
    12. 2.12 POD Interconnect
    13. 2.13 CK and ADDR_CTRL Topologies and Routing Guidance
    14. 2.14 Data Group Topologies and Routing Guidance
    15. 2.15 CK and ADDR_CTRL Routing Specification
      1. 2.15.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.15.2 CK and ADDR_CTRL Routing Limits
    16. 2.16 Data Group Routing Specification
      1. 2.16.1 DQLM - DQ Longest Manhattan Distance
      2. 2.16.2 Data Group Routing Limits
    17. 2.17 Bit Swapping
      1. 2.17.1 Data Bit Swapping
      2. 2.17.2 Address and Control Bit Swapping
  4. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  Net Classes
    8. 3.8  LPDDR4 Signal Termination
    9. 3.9  LPDDR4 VREF Routing
    10. 3.10 LPDDR4 VTT
    11. 3.11 CK and ADDR_CTRL Topologies
    12. 3.12 Data Group Topologies
    13. 3.13 CK and ADDR_CTRL Routing Specification
    14. 3.14 Data Group Routing Specification
    15. 3.15 Channel, Byte, and Bit Swapping
  5. 4Revision History

3.13 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin for the ADDR_CTRL nets. Thus, this skew must be controlled. The routed PCB track has a delay proportional to its length. Thus, the delay skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock.

Table 3-6 lists the limits for the individual segments that comprise the routing from the processor to the SDRAM. These segment lengths coincide with the CK and ADDR_CTRL topology diagram shown previously in Figure 3-4 and Figure 3-5. By matching the length for the same segments of all signals in a routing group, the signal delay skews are controlled. Most PCB layout tools can be configured to generate reports to assist with this validation. If this cannot be generated automatically, this must be generated and verified manually.

Table 3-6 CK and ADDR_CTRL Routing Specifications
Number Parameter MIN MAX UNIT
LP4_ACRS1 Propagation delay of net class CK, RSAC1 500(1) ps
LP4_ACRS2 Propagation delay of net class ADDR_CTRL, RSAC2 500(1) ps
LP4_ACRS3 Skew within net class CK (DDR0_CK0 to DDR0_CK0_n Skew) 0.4 ps
LP4_ACRS4 Skew across net class ADDR_CTRL (RSAC2) 3 ps
LP4_ACRS5 Skew across ADDR_CTRL net class and associated CK clock net class (RSAC1 to RSAC2) 3 ps
LP4_ACRS6 Vias per trace 3(1) vias
LP4_ACRS7 Via count difference 1(2) vias
LP4_ACRS8 Center-to-center CK to other LPDDR4 trace spacing(3) 4w
LP4_ACRS9 Center-to-center ADDR_CTRL to other LPDDR4 trace spacing(3) 4w
LP4_ACRS10 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(3) 3w
LP4_ACRS11 CK center-to-center spacing(4)(5) See notes below
LP4_ACRS12 CK spacing to other net(3) 4w
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
(3) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints).
(4) CK spacing set to ensure proper differential impedance.
(5) The user must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.