SPRACU8B August   2021  – January 2023 AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA829V , DRA829V , TDA4VM , TDA4VM

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
      1. 1.1.1 Supported Features (version 0.10.0)
      2. 1.1.2 Unsupported Features (version 0.10.0)
    2. 1.2 Spreadsheet Overview
      1. 1.2.1 Input Worksheets
      2. 1.2.2 Output Worksheets
      3. 1.2.3 Other Worksheets
    3. 1.3 Default SDK Configurations
  4. 2Customizing DDR Configuration
    1. 2.1 Config Worksheet
      1. 2.1.1 System Configuration
      2. 2.1.2 Memory Burst Configuration
    2. 2.2 DRAMTiming Worksheet
      1. 2.2.1 Latency Parameters
      2. 2.2.2 Non-Latency Parameters
    3. 2.3 IO Control Worksheet
      1. 2.3.1 Determining IO Settings
      2. 2.3.2 Processor/DDR Controller IO
      3. 2.3.3 DRAM I/O
  5. 3Software Considerations
    1. 3.1 Updating U-Boot
      1. 3.1.1 Updating DDR Register Settings
      2. 3.1.2 Updating Source to Set Available Memory Size
    2. 3.2 Updating RTOS PDK
      1. 3.2.1 Updating DDR Register Settings
  6. 4Troubleshoot Guide
    1. 4.1 Topics/Issues
      1. 4.1.1 Topic 1
      2. 4.1.2 Topic 2
      3. 4.1.3 Topic 3
  7. 5References
  8.   Revision History

2.3.3 DRAM I/O

Additional details of each parameter of this section can be found in the list below:

  1. VREF Control:
    1. VREF Range (DQ or CA): This parameter corresponds to MR14[6] for DQ signals and MR12[6] for command / address signals, and defines which VREF range is used for the respective signals.
    2. VREF (DQ or CA): This parameter corresponds to MR14[5:0] for DQ signals and MR12[5:0] for command / address signals, and defines the target reference voltage level, as a percentage of the I/O voltage.
  2. Drive Strength:
    1. Pull-Down (PDDS): This parameter corresponds to MR3[5:3] of the LPDDR4 memory and defines the drive strength of the DDR data (DQ) and strobe (DQS) pins during READ cycles. As discussed in Section 2.3.1, the appropriate value should be selected based on the I/O model settings used to achieve the best simulation results.
    2. Pull Up Calibration: This parameter corresponds to MR3[0] of the LPDDR4 memory and defines the target VOH during READ cycles. It is recommended to leave this parameter set to the default, "VDDQ / 3".
  3. Termination:
    1. CA ODT Disable: This parameter corresponds to MR22[5] of the LPDDR4 memory. When this parameter is set to "Disable", the termination of the command / address pins are disabled regardless of how the termination is configured in MR11 or the state of the ODT_CA pin. When this parameter is set to "ODT_CA Bond Pad", the termination of the command / address pins are configured based on the MR11 configuration along with the ODT_CA pin. It is recommended to leave this parameter set to the default, "ODT_CA Bond Pad".
    2. CK ODT Override: This parameter corresponds to MR22[3] of the LPDDR4 memory. When set to "Enable", the clock termination is determined by the MR11 configuration regardless of the ODT_CA pin. This parameter is used to enable termination on the clock when the CA bus is shared between two ranks, but the clock is not. Because the Jacinto 7 processors share both the CA bus and clock between ranks, it is recommended to leave this parameter set to the default, "Disable".
    3. CS ODT Override: This parameter corresponds to MR22[4] of the LPDDR4 memory. When set to "Enable", the chip select termination is determined by the MR11 configuration regardless of the ODT_CA pin. This parameter is used to enable termination on the chip select pin when the CA bus is shared between two ranks, but the chip select is not. Because the Jacinto 7 processors share the CA bus between ranks but have unique chip select signals, it is recommended to leave this parameter set to the default, "Enable".
    4. CA ODT: This parameter corresponds to MR11[6:4] of the LPDDR4 memory and defines the termination of the command / address pins of the LPDDR4 memory. As discussed in Section 2.3.1, the appropriate value should be selected based on the I/O model settings used to achieve the best simulation results.
    5. DQ ODT: This parameter corresponds to MR11[2:0] of the LPDDR4 memory and defines the termination of the data (DQ), data mask (DM), and strobe (DQS) pins of the LPDDR4 memory during WRITE cycles. As discussed in Section 2.3.1, the appropriate value should be selected based on the I/O model settings used to achieve the best simulation results.
    6. SOC ODT: This parameter corresponds to MR22[2:0] of the LPDDR4 memory and defines the termination of the processor / DDR controller. This parameter must be configured to match the termination as defined in 3.