In Section 4.2, a simple simulation was presented for the response of a dedicated ADC design to a single input step. However, simulation can also be used to evaluate the settling performance using an AC source. This allows for investigation of how the settling performance changes with increasing input frequency.

Before proceeding, it may be useful to first review the methods for performing an AC Input Simulation presented in the TI Precision Labs video: Final SAR ADC Drive Simulations.

Figure 4-4 shows the simulation setup for the AC simulation. The 400 V DC input source has been replaced with a 400 Vpp sine input. On the top, a duplicate of the original circuit, minus the sampling, has been added. This is necessary to generate a reference waveform that the sampled voltage can be compared to. If the input source is used directly for comparison the phase delay from the various R-C components will obscure the settling error.

Figure 4-5 shows the results of simulating a 60Hz AC input over many samples over 1 ms. Selecting an arbitrary sample while the sine wave is rising and examining the error waveform shows a settling error of about 0.2 mV right at the end of the S+H window. This level of settling error indicates the circuit is achieving good settling performance with a 60Hz input (1/2 LSB with a 3.0 V range is 0.37 mV).

Compared to the 60Hz input, Figure 4-6 shows the results of instead simulating with a 6kHz input. Taking the error at the end of the S+H period while the waveform is decreasing shows a settling error of approximately 19 mV, so the circuit does not perform very well when trying to track a much faster input. Note, however, that increasing the external ADC pin capacitor, C_S, improves the settling performance at higher speeds. Care needs to be taken to ensure C_S is not made so large that the 6 kHz input is attenuated by the low-pass filter formed by C_S and R_S.

In addition to the settling error increasing with increasing ADC input frequency, another important property of the settling error to note is that faster moving portions of the input signal will have increased error when compared to slower moving portions of the signal. Because of this, the settling error will not equally affect all portions of the input sine wave, resulting in the sampled waveform being distorted.