6 Test Results

The delayed protection scheme with CLB has been validated with the LaunchPad LAUNCHXL-F280049C. In the given example code, changing positive_cycle to 1 or 0 to decide positive cycle or negative cycle operation; changing EPWM8_Cmpa value to simulate different time scale for the trip signal; changing trip_within_one_cycle to simulate different types of trip signals, including sustaining within or across one EPWM cycle. It has been validated for single phase NPC inverter and extending to 3 phase NPC inverter.

The test results were measured with Kingst Logic Analyzer, as shown in Figure 6-1. And the related pin mapping information in this example is shown in Table 6-1.

Figure 6-2 shows the condition of trip during positive cycle, where EPWM1A starts CBC protection right at the trip low moment, while EPWM1B turns low after a delay of 1.035 μs. It was well matched with the defined 1 µs, considering the extra timing required by the internal hardware logic. Figure 6-3 shows the trip signal during negative cycle, where the delayed protection logic works as expected.

Figure 6-4 shows the waveforms of EPWM5 and EPWM6 in normal operation during positive cycle, with both rising edge delay and falling edge delay of 1 µs defined. And EPWM5B and EPWM6B measured are not the initial EPWMxB, but the signals after the CLB module. It shows that the dead time between EPWM5A and EPWM5B is 1.025 μs and 0.975 μs, thus the delay induced by the CLB module should be acceptable.

Figure 6-5 and Figure 6-6 show the waveform of EPWM5 and EPWM6 with trip signal during positive cycle and negative cycle, respectively.