SPRACZ9A November   2021  – December 2022 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Hardware Design Guide for F2800x Devices
  2.   Trademarks
  3. 1Introduction
  4. 2Typical F2800x System Block Diagram
  5. 3Schematic Design
    1. 3.1 Package and Device Decision
      1. 3.1.1 F2800x Devices
        1. 3.1.1.1 TMS320F28004x
        2. 3.1.1.2 TMS320F28002x
        3. 3.1.1.3 TMS320F28003x
        4. 3.1.1.4 TMS320F280013x
      2. 3.1.2 Migration Guides
      3. 3.1.3 PinMux Tool
      4. 3.1.4 Configurable Logic Block
    2. 3.2 Digital IOs
      1. 3.2.1 General Purpose Input/Outputs
      2. 3.2.2 Integrated Peripherals and X-BARs
      3. 3.2.3 Control Peripherals
      4. 3.2.4 Communication Peripherals
      5. 3.2.5 Boot Pins and Boot Peripherals
    3. 3.3 Analog IOs
      1. 3.3.1 Analog Peripherals
      2. 3.3.2 Choosing Analog Pins
      3. 3.3.3 Internal vs. External Analog Reference
      4. 3.3.4 ADC Inputs
      5. 3.3.5 Driving Options
      6. 3.3.6 Low-Pass/Anti-Aliasing Filters
    4. 3.4 Power Supply
      1. 3.4.1 Power Requirements
      2. 3.4.2 Power Sequencing
      3. 3.4.3 VDD Voltage Regulator
        1. 3.4.3.1 Internal vs. External Regulator
        2. 3.4.3.2 Internal LDO vs. Internal DC-DC Regulator
      4. 3.4.4 Power Consumption
      5. 3.4.5 Power Calculations
    5. 3.5 XRSn and System Reset
    6. 3.6 Clocking
      1. 3.6.1 Internal vs. External Oscillator
    7. 3.7 Debugging and Emulation
      1. 3.7.1 JTAG/cJTAG
      2. 3.7.2 Debug Probe
    8. 3.8 Unused Pins
  6. 4PCB Layout Design
    1. 4.1 Layout Design Overview
      1. 4.1.1 Recommend Layout Practices
      2. 4.1.2 Board Dimensions
      3. 4.1.3 Layer Stack-Up
    2. 4.2 Recommended Board Layout
    3. 4.3 Placing Components
      1. 4.3.1 Power Electronic Considerations
    4. 4.4 Ground Plane
    5. 4.5 Analog and Digital Separation
    6. 4.6 Signal Routing With Traces and Vias
    7. 4.7 Thermal Considerations
  7. 5EOS, EMI/EMC, and ESD Considerations
    1. 5.1 Electrical Overstress
    2. 5.2 Electromagnetic Interference and Electromagnetic Compatibility
    3. 5.3 Electrostatic Discharge
  8. 6Final Details and Checklist
  9. 7References
  10. 8Revision History

3.4.5 Power Calculations

Calculating the required power supply sizing requires taking into consideration the loads that plan to be present on the power supply, the noise tolerated by the system, as well as overall current requirements.

Firstly, calculate the current requirement for each voltage rail. Be sure to add the peak current values for each chip/module, which is typically each power supply pin. Additionally, plan to also account for all other passive and active loads, which include components such as LEDs and other loads.

For added precaution and to ensure a safe design, multiply these currents by a value between 1.3 to 2 to arrive at the recommend current specifications of the voltage regulator. This avoids current-starving any blocks connected to the power supply system. Select between the choice of linear regulators and DC-DC converters. This decision primarily depends on the amount of power supply noise tolerated by the system as a whole. In systems that require very low noise, linear regulators/LDOs are recommended. DC-DC converters, on the other hand, offer better power efficiency.

The following scenarios provide example guidance on calculating the recommend power supply specifications:

  • An application makes use of F28002x and all of its available peripherals. The device’s flash will not be upgraded in the field, ten of its GPIO pins will drive 1.5 mA static loads, and two additional GPIOs are toggling waveforms at 200 kHz with a 10 pF load.
    Equation 1. P e s t = { O p e r a t i n g   M o d e } + n G P I O , s t a t i c × l l o a d + n G P I O , a c t i v e × n t r a n s i t i o n s / p e r i o d × f × C × V 2
    Equation 2. P e s t = 0.072 A + 0.005 A + 10 × 0.0015 A + 2 × 2 × 200 k × 10 p × 3.3 2
    Equation 3. P e s t = 92 m A

    In this scenario, though flash-programming will not occur in the field, initial programming will occur. Thus:

    Equation 4. 92 m A < 106 m A + 2.5 m A = 108.5 m A

    Multiplying by a margin value of 1.5, the final supply current requirement is determined:

    Equation 5. 108.5 m A × 1.5 = 162 m A   @   3.3 V   535 m W
  • An application uses the F28002x and the following peripherals: two ADCs, one CAN, and four HRPWM modules. It will need to be upgraded in the field.
    Equation 6. P e s t = { F l a s h   P r o g r a m   M o d e } + ( 2 × I A D C ) + ( 1 × I C A N ) + ( 4 × I H R P W M )
    Equation 7. P e s t = 0.106 A + 0.0025 A + 2 × 0.67 A + 1 × 1.18 A + 4 × 0.87 A
    Equation 8. P e s t = 114 m A

    Multiplying by a margin value of 1.5, we arrive at our final supply current requirement:

    Equation 9. 114 m A × 1.5 = 171 m A   @   3.3 V   564 m W