SPRACZ9A November   2021  – December 2022 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Hardware Design Guide for F2800x Devices
  2.   Trademarks
  3. 1Introduction
  4. 2Typical F2800x System Block Diagram
  5. 3Schematic Design
    1. 3.1 Package and Device Decision
      1. 3.1.1 F2800x Devices
        1. 3.1.1.1 TMS320F28004x
        2. 3.1.1.2 TMS320F28002x
        3. 3.1.1.3 TMS320F28003x
        4. 3.1.1.4 TMS320F280013x
      2. 3.1.2 Migration Guides
      3. 3.1.3 PinMux Tool
      4. 3.1.4 Configurable Logic Block
    2. 3.2 Digital IOs
      1. 3.2.1 General Purpose Input/Outputs
      2. 3.2.2 Integrated Peripherals and X-BARs
      3. 3.2.3 Control Peripherals
      4. 3.2.4 Communication Peripherals
      5. 3.2.5 Boot Pins and Boot Peripherals
    3. 3.3 Analog IOs
      1. 3.3.1 Analog Peripherals
      2. 3.3.2 Choosing Analog Pins
      3. 3.3.3 Internal vs. External Analog Reference
      4. 3.3.4 ADC Inputs
      5. 3.3.5 Driving Options
      6. 3.3.6 Low-Pass/Anti-Aliasing Filters
    4. 3.4 Power Supply
      1. 3.4.1 Power Requirements
      2. 3.4.2 Power Sequencing
      3. 3.4.3 VDD Voltage Regulator
        1. 3.4.3.1 Internal vs. External Regulator
        2. 3.4.3.2 Internal LDO vs. Internal DC-DC Regulator
      4. 3.4.4 Power Consumption
      5. 3.4.5 Power Calculations
    5. 3.5 XRSn and System Reset
    6. 3.6 Clocking
      1. 3.6.1 Internal vs. External Oscillator
    7. 3.7 Debugging and Emulation
      1. 3.7.1 JTAG/cJTAG
      2. 3.7.2 Debug Probe
    8. 3.8 Unused Pins
  6. 4PCB Layout Design
    1. 4.1 Layout Design Overview
      1. 4.1.1 Recommend Layout Practices
      2. 4.1.2 Board Dimensions
      3. 4.1.3 Layer Stack-Up
    2. 4.2 Recommended Board Layout
    3. 4.3 Placing Components
      1. 4.3.1 Power Electronic Considerations
    4. 4.4 Ground Plane
    5. 4.5 Analog and Digital Separation
    6. 4.6 Signal Routing With Traces and Vias
    7. 4.7 Thermal Considerations
  7. 5EOS, EMI/EMC, and ESD Considerations
    1. 5.1 Electrical Overstress
    2. 5.2 Electromagnetic Interference and Electromagnetic Compatibility
    3. 5.3 Electrostatic Discharge
  8. 6Final Details and Checklist
  9. 7References
  10. 8Revision History

3.2.1 General Purpose Input/Outputs

The TMS320F2800x microcontrollers contain varying numbers of general purpose I/O (GPIO) pins. They serve as the digital inputs and outputs of the device, and these GPIO-enabled pins can be configured to be used either as typical GPIOs or as peripheral I/O signals. This design grants great flexibility when using the C2000 devices in different applications. Up to 12 independent peripheral signals are multiplexed on a single GPIO-enabled pin, and the same peripheral can be multiplexed onto multiple GPIO pins.

For each GPIO-pin, the max drive strength (sink/source current) is 4 mA. The maximum toggling frequency for F28002x/F28004x is 25 MHz with a rise/fall time of 8 ns. Note for F28004x, this applies to all GPIOs except for GPIO23_VSW. For F280013x/F28003x, this maximum toggling frequency is 50 MHz with the same rise/fall time of 8 ns.

GUID-20210414-CA0I-VXPQ-BWP1-3SQTKH0CTQVT-low.gifFigure 3-4 GPIO Output Timing

At reset, the GPIO pins are defined as inputs, and they all have internal pull-ups which are disabled on device boot and at reset. These pull-ups can be selectively enabled or disabled through software. To avoid any floating unbonded inputs, the Boot ROM will automatically enable internal pullups on GPIO pins that are not bonded out in a particular package. Additionally, all GPIO pins are high-impedance during device boot and until they are configured in firmware. This means that PWM signals, relay drivers, chip selects, and so forth should have external pull-resistors to enforce a state during power-up.

As an additional feature, GPIO inputs allow the user to filter out any unwanted noise glitches through input qualification. There are three available options for input qualification: no synchronization (asynchronous input), synchronization to SYSCLKOUT, and qualification using a sampling window. Pins that are configured as peripheral inputs can be configured with any of the three options. The GPIO-configured pins only have access to SYSCLKOUT synchronization and qualification using a sampling window. More detailed information about this feature and how to design around it can be found in the Input Qualification section of the device-specific Technical Reference Manuals.

In addition to configuring the pin selection of the device, it is also essential to be aware of best practices when making use of the general purpose I/O (GPIO) resources on the device. C2000 devices continually integrate more onboard analog peripherals, like ADCs, DACs, PGAs, and CMPSSs, which help to reduce system level cost. These additional peripherals, however, lead to reduced GPIO availability when trying to maintain similar pin-packages. Thus, it is important to maximize GPIO usage when designing a custom system. TI offers a guide on How to Maximize GPIO Usage in C2000 Devices that provides common suggestions on GPIO usage and how to reduce the need for IO expanders.