SPRACZ9A November   2021  – December 2022 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Hardware Design Guide for F2800x Devices
  2.   Trademarks
  3. 1Introduction
  4. 2Typical F2800x System Block Diagram
  5. 3Schematic Design
    1. 3.1 Package and Device Decision
      1. 3.1.1 F2800x Devices
        1. 3.1.1.1 TMS320F28004x
        2. 3.1.1.2 TMS320F28002x
        3. 3.1.1.3 TMS320F28003x
        4. 3.1.1.4 TMS320F280013x
      2. 3.1.2 Migration Guides
      3. 3.1.3 PinMux Tool
      4. 3.1.4 Configurable Logic Block
    2. 3.2 Digital IOs
      1. 3.2.1 General Purpose Input/Outputs
      2. 3.2.2 Integrated Peripherals and X-BARs
      3. 3.2.3 Control Peripherals
      4. 3.2.4 Communication Peripherals
      5. 3.2.5 Boot Pins and Boot Peripherals
    3. 3.3 Analog IOs
      1. 3.3.1 Analog Peripherals
      2. 3.3.2 Choosing Analog Pins
      3. 3.3.3 Internal vs. External Analog Reference
      4. 3.3.4 ADC Inputs
      5. 3.3.5 Driving Options
      6. 3.3.6 Low-Pass/Anti-Aliasing Filters
    4. 3.4 Power Supply
      1. 3.4.1 Power Requirements
      2. 3.4.2 Power Sequencing
      3. 3.4.3 VDD Voltage Regulator
        1. 3.4.3.1 Internal vs. External Regulator
        2. 3.4.3.2 Internal LDO vs. Internal DC-DC Regulator
      4. 3.4.4 Power Consumption
      5. 3.4.5 Power Calculations
    5. 3.5 XRSn and System Reset
    6. 3.6 Clocking
      1. 3.6.1 Internal vs. External Oscillator
    7. 3.7 Debugging and Emulation
      1. 3.7.1 JTAG/cJTAG
      2. 3.7.2 Debug Probe
    8. 3.8 Unused Pins
  6. 4PCB Layout Design
    1. 4.1 Layout Design Overview
      1. 4.1.1 Recommend Layout Practices
      2. 4.1.2 Board Dimensions
      3. 4.1.3 Layer Stack-Up
    2. 4.2 Recommended Board Layout
    3. 4.3 Placing Components
      1. 4.3.1 Power Electronic Considerations
    4. 4.4 Ground Plane
    5. 4.5 Analog and Digital Separation
    6. 4.6 Signal Routing With Traces and Vias
    7. 4.7 Thermal Considerations
  7. 5EOS, EMI/EMC, and ESD Considerations
    1. 5.1 Electrical Overstress
    2. 5.2 Electromagnetic Interference and Electromagnetic Compatibility
    3. 5.3 Electrostatic Discharge
  8. 6Final Details and Checklist
  9. 7References
  10. 8Revision History

Internal vs. External Oscillator

An important decision in the design process is choosing whether to make use of the on-board clocking options or incorporating an external oscillator into the system. The following design considerations should provide ample assistance in the decision-making process, although the final choice is dependent on cost and system-clocking requirements.

The two internal 0-pin on-chip oscillators (INTOSC1 and INTOSC2) run at 10 MHz and can be used to provide clock for the main PLL and CPU-Timer 2. In addition, INTOSC1 can also provide clock for the watchdog block. These oscillators are both enabled by default at power up, where INTOSC2 is set as the source for the system reference clock and INTOSC1 Is used as the backup clock source. This clocking option is useful for designs which prioritize cost-savings and shorter design schedules. The trade-off with this decision is lower accuracy compared to an external clock source. Depending on the environmental conditions, the clock could have frequency stability of approximately 1.5% to 3% outside of the typical 10 MHz. The stability is different for every device, so see the device-specific data sheet for the specific values and test conditions. Additionally, note that for F28004x, GPIO18 and its mux options are only available when the system is clocked by INTOSC and X1 has an external pull-down resistor. For the other devices, GPIO18 and GPIO19 can be used as additional digital signals when INTOSC is used.

Another clocking option is using the internal oscillator in conjunction with an external crystal. This approach should be used if clocking precision better than 1% is required. An important consideration when choosing this approach is that making any other additional connections to the crystal circuit is not recommended. Additionally, the crystal oscillator needs to be designed very carefully to ensure proper function. These crystals have multiple parameters, so it is recommended to consult with crystal vendors to incorporate a crystal that works well with the C2000 device. Special attention must be placed so that the crystal chosen accurately matches the load capacitance for the system. A crystal with a load capacitance Cload outside of the ideal range will inhibit the oscillator driving the crystal from starting up and running reliably. The effective load capacitance appears as the series combination of C1 and C2, which are the capacitors connected to X1 and X2, respectively. To calculate the value for Cload, take into consideration C1 and C2 as well as stray capacitance for routing on the PCB.

Equation 10. C l o a d , X T A L = C 1 × C 2 C 1 + C 2 + C s t r a y

Assume C1 and C2 are equivalent. This is not a requirement, but aids in simplifying the calculation to the following equation:

Equation 11. C l o a d , X T A L = C 2 + C s t r a y

For example, suppose a system has known load capacitance of 12 pF and stray capacitance of 2 pF. Appropriate calculations give a suggested capacitor value of 20 pF.

Equation 12. 12 p F = C 2 + 2 p F
Equation 13. C = 20 p F

For current F2800x devices, the recommended crystal load capacitance should be around 12 pF to 24 pF. In future devices, this value may be different. For additional requirements, see the device-specific data sheet. As shown in Figure 3-13, the crystal should be connected across X1 and X2 with its load capacitors connected to VSS.

Figure 3-13 External Crystal Circuit

A resonator may also be used in a similar fashion as the crystal and offers similar tradeoffs and considerations. When implementing the resonator, it should be connected across X1 and X2 with the ground connected to VSS, as shown in Figure 3-14.

Figure 3-14 External Resonator Circuit

A third and final clocking source option is using an external oscillator completely. This is a simpler approach than using an external crystal and can provide the most accuracy for real-time systems. Furthermore, other devices within the system can share the clock signal being output from the external oscillator. The clock signal should be connected to the MCU as shown in Figure 3-15, with the output of the external oscillator connected to X1 and the XTALCR.SE bit set to 1.

Figure 3-15 External Oscillator Circuit