SPRACZ9A November 2021 – December 2022 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
As mentioned earlier, each peripheral signal is multiplexed to many GPIO pins to ease the design and layout process and allow for maximal flexibility. For a detailed table listing all of the available GPIO peripheral pin configurations, see the Pin Attributes table in the data sheet for each device.
To route the signals from a GPIO to any of the different IP blocks—such as the ADCs, eCAPs, ePWMs, and external interrupts—the devices make use of input crossbars (X-BAR). The Input X-BAR has access to every GPIO and can route each signal to any (or multiple) of the IP blocks mentioned previously, as well as the digital input sides of the AIOs. In essence, the Input X-BARs give the ability to route the output of one peripheral to another. These C2000 MCU devices also contain GPIO Output X-BARs, which take signals from inside the device and bring them out to a GPIO.
Apart from these two crossbars, each device also contains two other kinds of X-BARs: ePWM X-BARs and CLB X-BARs. As the names imply, the ePWM X-BAR is responsible for routing signals into the ePWM modules and CLB X-BAR is responsible for routing signals to the CLB. The CLB itself also has access to CLB INPUT X-BAR and CLB OUTPUT X-BAR, which enable the ability to route signals from the GPIO pins to the CLB as inputs or outputs. The ePWM X-BAR is connected to the Digital Compare (DC) submodule of each ePWM module for actions such as tripzones and syncing.