A cycle-by-cycle (CBC) trip is used for current limiting operations. When a cycle-by-cycle trip is detected, the trip-zone submodule drives EPWMxA and EPWMxB to a certain specified state. The outputs go back to their pre-trip state at the next ZRO, PRD, or ZRO/PRD events.

A comparator from the comparator subsystem (CMPSS) is set up to cause a trip event that then generates a CBC trip on EPWM2.

The CMPSS consists of analog comparators and supporting circuits that are useful for power applications. The comparators have a positive and negative input. A high digital output is generated when the voltage on the positive input is greater than the voltage on the negative input, and a low digital output when the voltage on the positive input is less than the voltage on the negative input.

Figure 7-1 Comparator Block Diagram

In order to cause a high digital output, a trip condition needs to occur when the positive input (voltage A) is greater than the negative input (voltage B). Therefore, the positive input is connected to an external voltage source that you need to monitor to make sure it does not exceed a certain state. The negative input can come from the reference digital-to-analog converter (DAC) on the device. For this application, a value of 2500 is written to DACVALA, the value driven to the negative terminal.

The ideal output of the reference 12-bit DAC can be calculated as:

Applying the known values, you get a DACOUT value of 2 V. Therefore, whenever the voltage applied to the positive input of the comparator exceeds 2 V, the trip signal is asserted.

Comparator 1 is utilized for this use-case. #FIG_OGT_FDV_4TB displays the setup for the CMPSS1 module based on the above calculation.

The following code is generated from SysConfig for the CMPSS configuration:

void CMPSS_init(){
// myCMPSS1 initialization
// Sets the configuration for the high comparator. 
CMPSS_configHighComparator(myCMPSS1_BASE,(CMPSS_INSRC_DAC));
// Sets the configuration for the high comparator. 
CMPSS_configLowComparator(myCMPSS1_BASE,(CMPSS_INSRC_DAC));
// Sets the configuration for the internal comparator DACs. 
CMPSS_configDAC(myCMPSS1_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW));
// Sets the value of the internal DAC of the high comparator. 
CMPSS_setDACValueHigh(myCMPSS1_BASE,2500U);
// Sets the value of the internal DAC of the low comparator. 
CMPSS_setDACValueLow(myCMPSS1_BASE,0U);
// Configures the digital filter of the high comparator. 
CMPSS_configFilterHigh(myCMPSS1_BASE, 0U, 1U, 1U);
// Configures the digital filter of the low comparator. 
CMPSS_configFilterLow(myCMPSS1_BASE, 0U, 1U, 1U);
// Sets the output signal configuration for the high comparator. 
CMPSS_configOutputsHigh(myCMPSS1_BASE,(CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_ASYNC_COMP));
// Sets the output signal configuration for the low comparator. 
CMPSS_configOutputsLow(myCMPSS1_BASE,(CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_ASYNC_COMP));
// Sets the comparator hysteresis settings. 
CMPSS_setHysteresis(myCMPSS1_BASE,0U);
// Configures the comparator subsystem's ramp generator. 
CMPSS_configRamp(myCMPSS1_BASE,0U,0U,0U,1U,true);
// Disables reset of HIGH comparator digital filter output latch on PWMSYNC 
CMPSS_disableLatchResetOnPWMSYNCHigh(myCMPSS1_BASE);
// Disables reset of LOW comparator digital filter output latch on PWMSYNC 
CMPSS_disableLatchResetOnPWMSYNCLow(myCMPSS1_BASE);
// Sets the ePWM module blanking signal that holds trip in reset. 
CMPSS_configBlanking(myCMPSS1_BASE,1U);
// Disables an ePWM blanking signal from holding trip in reset. 
CMPSS_disableBlanking(myCMPSS1_BASE);
// Configures whether or not the digital filter latches are reset by PWMSYNC 
CMPSS_configLatchOnPWMSYNC(myCMPSS1_BASE,false,false);
// Enables the CMPSS module. 
CMPSS_enableModule(myCMPSS1_BASE);
// Delay for CMPSS DAC to power up. 
DEVICE_DELAY_US(500);
}

It is important to note that the external signal applied to the positive input of the comparator needs to remain for a minimum of 3*TBCLK for the signal to be properly detected and cause a trip condition.

There is no direct path from the comparator subsystem to the trip zone submodule of the ePWM submodule, therefore the digital compare submodule must be utilized to route the signal. In order to figure out how to properly route the CMPSS signal through the digital compare submodule, you must first start with the ePWM X-BAR. The TRM of each device has a table that describes the mux positioning of the ePWM X-BAR, known as “ePWM X-BAR Mux Configuration Table”. #GUID-03FCFA41-747E-4F6E-8306-A10ABC3D5ADE shows an example of an ePWM X-BAR configuration table. From #GUID-51A414E5-D471-411A-8B38-5C013FDD598C, you can see that `CMPSS1.CTRIPH` is in position 0 of Mux 0. From the Input X-BAR configuration, you can route this to any trip signal between 4 and 12; for this application, Trip 4 is chosen.

#FIG_S14_13V_4TB shows how to configure the ‘EPWMXBAR’ within the system options of SysConfig.

The following code is generated from SysConfig:

void EPWMXBAR_init(){
//myEPWMXBAR4 initialization 
XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH); 
XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
}

The DC submodule can generate up to four events DCAEVT1, DCAEVT2, DCBEVT1, and DCBEVT2. Only event 2 can cause a cycle-by-cycle trip, so you need to focus on DCAEVT2 for this application use-case. The digital compare event has a high (DCAH) and low (DCAL) signal. These two signals can be used to cause DCAEVT2. For this case, route the CMPSS1 output to either of the two signals since you only need one. DCAH was chosen. The condition in which the event is generated is when this signal goes high, meaning the value applied to the comparator’s positive input is above the voltage at the negative input.

The following code is generated from SysConfig:

EPWM_selectDigitalCompareTripInput(myEPWM2_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH); 
EPWM_setTripZoneDigitalCompareEventCondition(myEPWM2_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);

You can now set up the trip-zone settings to drive both A and B outputs to a low state through a cycle by cycle trip whenever there is a DCAEVT2 event. An interrupt is also generated whenever the trip occurs to allow you to clear the flags.

The following code is generated from SysConfig:

EPWM_setTripZoneAction(myEPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); 
EPWM_setTripZoneAction(myEPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); 
EPWM_enableTripZoneSignals(myEPWM2_BASE, EPWM_TZ_SIGNAL_DCBEVT2); 

void epwm2TZISR(void){
    epwm2TZIntCount++;

    // Clear the flags
    EPWM_clearTripZoneFlag(myEPWM2_BASE, (EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_CBC));

    // Acknowledge this interrupt to receive more interrupts from group 2
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP2);
}

After configuring EPWM2 to have a trip condition when a positive voltage of greater than 2 V is applied to the positive input on comparator 1, EPWM2 should be driven low.