SPRAD12A July   2022  – February 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SJ , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 SysConfig
  5. 3 Time-Base (TB) Submodule
    1. 3.1 Setting the Frequency
    2. 3.2 Applying a Phase Shift
    3. 3.3 Setting up the Synchronization (Sync) Scheme
  6. 4 Counter-Compare (CC) and Action-Qualifier (AQ) Submodules
    1. 4.1 Calculating the Duty Cycle
  7. 5 Deadband (DB) Submodule
    1. 5.1 Setting up Signal Pairs
  8. 6 Verifying the Output
    1. 6.1 Checking the Duty Cycle and Dead-Time Insertion
    2. 6.2 Checking the Phase Shift Applied
  9. 7 Trip-Zone (TZ) and Digital Compare (DC) Submodules
    1. 7.1 Drive Outputs Low for an ePWM Cycle Upon Trip Condition Set Through CMPSS
    2. 7.2 Drive Outputs Low Until Cleared Through Software Upon Trip Condition set Through GPIO
  10. 8 Event-Trigger (ET) Submodule
    1. 8.1 Setting Up Time-Base Interrupts
  11. 9 Global Load
    1. 9.1 Applying Global Loading and One-Shot Load Feature
    2. 9.2 Linking the ePWM Modules
    3. 9.3 Updating Action Qualifier Settings and Counter Compare Values Through Global Loading
  12. 10Summary
  13. 11References
  14. 12Revision History

4.1 Calculating the Duty Cycle

One of the requirements for this use-case is having an initial 45% duty cycle. The duty cycle of each ePWM is based on the counter compare values and the actions taken whenever there is a counter compare match. As the time-base counter is incrementing or decrementing, it is constantly checking for a zero, counter compare, or period match. If there is a match, then the ePWM outputs can be programmed to go low (clear), go high (set), toggle, or do nothing.

In this case, the action qualifier events are defined in the following way:

For EPWMxA:

  • CMPA UP -> Set
  • CMPA DOWN -> Clear

For EPWMxB:

  • CMPB UP -> Set
  • CMPB DOWM -> Clear

#GUID-428157EB-EE01-482F-A9A6-D9E9ECC79DDF shows how to configure the AQ submodule. The global load feature is explained in GUID-6A9B0100-1498-4D36-A7DC-747E4F270BE9.html#GUID-6A9B0100-1498-4D36-A7DC-747E4F270BE9.

Figure 4-1 ePWM Action-Qualifier: Setting Global Load and Output Events

In order to get an initial 45% duty cycle, you need to determine what value to set for CMPA and CMPB.

Our time-base counter counts a total of 250 (2*125) times in one period since it counts both in the up and down direction. Due to the chosen settings, the waveform is “ON” for the duration of 2*(TBPRD-CMPA) for output A or 2*(TBPRD-CMPB) for output B. Based on this information, you can figure out the CMPA and CMPB values, abbreviated to CMPX.

In order to achieve an initial 45% duty cycle, CMPA and CMPB need to be set to 69 based upon the desired action qualifier events.

Figure 4-2 ePWM Counter-Compare: Setting the Counter Compare Values

The following code is generated from SysConfig:

// EPWM 1
EPWM_setCounterCompareValue(myEPWM1_BASE, EPWM_COUNTER_COMPARE_A, 69); 
EPWM_enableGlobalLoadRegisters(myEPWM1_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR); 
EPWM_setCounterCompareValue(myEPWM1_BASE, EPWM_COUNTER_COMPARE_B, 69); 
EPWM_enableGlobalLoadRegisters(myEPWM1_BASE, EPWM_GL_REGISTER_CMPB_CMPBHR);
// EPWM 2 (the code is the same for EPWM3, except for the base address)
EPWM_setCounterCompareValue(myEPWM2_BASE, EPWM_COUNTER_COMPARE_A, 69);  
EPWM_enableGlobalLoadRegisters(myEPWM2_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR);  
EPWM_setupEPWMLinks(myEPWM2_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);  
EPWM_setCounterCompareValue(myEPWM2_BASE, EPWM_COUNTER_COMPARE_B, 69);  
EPWM_enableGlobalLoadRegisters(myEPWM2_BASE, EPWM_GL_REGISTER_CMPB_CMPBHR);  
EPWM_setupEPWMLinks(myEPWM2_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_B);