SPRAD12A July 2022 – February 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SJ , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The Time-Base (TB) submodule is used to setup the ePWM modules with a frequency of 400 kHz. Each ePWM module has a time-base counter (TBCTR). There are three modes of the time-base counter: UP, DOWN, and UP-DOWN. The frequency of the PWM events ( ) is controlled by the time-base period (TBPRD) register and the mode of the time-base counter.
For up and down count modes:
For up-down count mode:
Where, is the period of the PWM events and is the period of the time-base clock. The time-base clock (TBCLK) is a prescaled version of the ePWM clock (EPWMCLK). This clock determines the rate at which the time-base counter increments and decrements.
For the use-case discussed in this application report, the up-down count mode is utilized as it provides more configurability options due to the symmetry of the count mode. Start by finding :
Now that you know what is, you can start calculating the value for TBPRD:
The time-base clock is defined through the following formula:
The maximum EPWMCLK is defined in the device-specific data sheet. EPWMCLK is usually the same as SYSCLK but some devices may have a clock divider, EPWMCLKDIV, which reduces the frequency of the ePWM clock. The high-speed clock divider (HSPCLKDIV) and the clock divider (CLKDIV) are programmable dividers used to help achieve a desired ePWM time-base clock. For this use-case, both clock dividers are set to divide by 1 and EPWMCLK is 100 MHz.
Now that you have all of the needed parameters, you can calculate the TBPRD value:
What this means is that the time-base counter counts from zero to 125 and then back to zero. This counts as one period of the ePWM output, resulting in a 400 kHz output frequency for EPWM1, EPWM2, and EPWM3.
The following code is generated from SysConfig:
// EPWM1 (the code is the same for EPWM2 and EPWM3, except for the base address)
EPWM_setClockPrescaler(myEPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(myEPWM1_BASE, 125);
EPWM_setTimeBaseCounterMode(myEPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);