SPRAD13A May   2022  – December 2024 AM623 , AM625

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Via Channel Arrays
  6. 3 Width/Spacing Proposal for Escapes
  7. 4 Stackup
  8. 5 Via Sharing
  9. 6 Floorplan Component Placement
  10. 7 Critical Interfaces Impact Placement
  11. 8 Routing Priority
  12. 9 SerDes Interfaces
  13. 10DDR Interfaces
  14. 11Power Decoupling
  15. 12Route Lowest Priority Interfaces Last
  16. 13Summary
  17. 14Revision History

3 Width/Spacing Proposal for Escapes

The AM62x Via channel array solution has been designed to support the following. AM62x package supports similar feature set as several other competition solutions with approx. 15% smaller package area and ~10% wider line width. This solution therefore, reduces PCB foot print and utilizes lower cost PCB rules enabling compact and low-cost systems.

Table 3-1 Width/Spacing Proposal for Escapes
PCB Feature PCB Routing Requirements
Minimum via diameter 18 mils
Via hole size 10 mils (0.25mm)
Minimum trace width/spacing required in the BGA break out 3.2mil / 3.2mil
Number of layers used for escape 3
BGA land pad size 0.25mm via (typical)
Package Size 13mm x 13mm, 0.5mm pitch w/ VCA
PCB layers (signal routing, total) recommended 2, 6