SPRAD13A May   2022  – December 2024 AM623 , AM625

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Via Channel Arrays
  6. 3 Width/Spacing Proposal for Escapes
  7. 4 Stackup
  8. 5 Via Sharing
  9. 6 Floorplan Component Placement
  10. 7 Critical Interfaces Impact Placement
  11. 8 Routing Priority
  12. 9 SerDes Interfaces
  13. 10DDR Interfaces
  14. 11Power Decoupling
  15. 12Route Lowest Priority Interfaces Last
  16. 13Summary
  17. 14Revision History

5 Via Sharing

The Via Channel Array BGA pattern implemented on the AM62 design offers several opportunities for via sharing. Vias are shared across BGA pins. Figure 5-1 and Figure 5-2 show the via sharing opportunities for VDDR_CORE and VSS domains, respectively. Figure 5-1 assumes that VDD_CORE and VDDR_CORE domains are separate. If these domains are merged, more via sharing opportunities are presented, as shown in Figure 5-3. Via sharing across BGA pins provides for easier escape routing and also stronger electrical connections by connecting multiple pins.

Via Sharing for VDDR_CORE Domain Figure 5-1 Via Sharing for VDDR_CORE Domain
Via Sharing for VSS Figure 5-2 Via Sharing for VSS
Via Sharing for Merged VDD_CORE and VDDR_CORE Domains Figure 5-3 Via Sharing for Merged VDD_CORE and VDDR_CORE Domains