SPRAD14 April 2022 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1
Jacinto TDA4x processors family is a scalable platform with software-compatible products. Based on systems requirements, TDA4x SoC family offers multiple products with different performance, power and feature-set that customers can choose from. Currently, the TDA4VM is production and details can be found at TDA4VM product page [1]. Table 1-1 shows a typical IP configuration of TDA4VM. For more information, see the DRA829/TDA4VM Technical Reference Manual [2].
Processor/Accelerator | Interface | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
TDA4VM | IP | Arm | Arm-R5F | DSP | GPU | MMA | DDR | Capture | PCIe | Ethernet |
Feature | 2xA72 (~25K DMIPS) |
3xDual R5F (3x ~12KDMIPS) |
1xC7x+ 2xC66x |
GE8430 (100 GFLOPs) |
1xMMAv1 8TOPs | 1x32b@4266Mhz | 2x CSI-Rx (4L) | PCIe Gen3: 4x 2DL | 8pswitch+ 1x RGMII (MCU) |
Dual-TDA4x cascading solution may be required in below scenarios:
All the Jacinto TDA4VM SoCs are configured with Ethernet and PCIe interfaces. This means that all the TDA4x family processors can be interconnected via Ethernet and PCIe to enable dual-SoC system requirements. Next sections will discuss system considerations for such solution.