SPRAD14 April   2022 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Dual TDA4 System
    1. 2.1 Dual TDA4x SoC System Diagram
    2. 2.2 System Consideration and BOM Optimization
  4. 3Camera Connection
    1. 3.1 Duplicate Front Camera Input to Two TDA4x SoCs
    2. 3.2 Connect Front Camera to Only one TDA4x
  5. 4Boot Sequence Solution
    1. 4.1 Boot Solution Based on Dual Flash
    2. 4.2 Boot Solution Based on Single Flash
  6. 5Multi-SoC Demo Based on PCIe
  7. 6References

Boot Solution Based on Single Flash

In this case, only one boot flash for primary TDA4 is used, as shown in Figure 4-2. The advantage of this boot sequence is lower system cost, and the disadvantage is longer system boot time because the secondary TDA4x SoC is dependent on the primary TDA4x SoC to start booting.

Figure 4-2 Boot Flow With First flash Only

Key features and process as below:

  • The primary TDA4x SoC uses OSPI/QSPI boot mode, meanwhile the secondary TDA4x SoC boots using SPI/USB/Eth/PCIe mod depending on hardware support.
  • Primary TDA4x SoC will boot from its own OSPI, then wakeup the secondary TDA4x PMIC via I2C connection, then initialize and configure the hardware interface which used to boot secondary TDA4x SoC. In parallel, it will load the boot images for other cores (except A72) from EMMC to DDR.
  • After PMIC is enabled, secondary TDA4x SoC will first receive boot image from primary TDA4x SoC and starts to boot. After that, it loads all of the core images from EMMC to DDR to boot the whole system.
  • After both TDA4x SoC boots are completed, subsequent data transfer can happen via Ethernet/PCIe.