General

Review and verify the following for the custom schematic design:

1. Above sections, including relevant application notes and FAQ links
2. Pin attributes, signal description, and electrical specifications
3. Electrical characteristics, timing parameters, and any additional available information
4. MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51)
5. The AM62Px processor family implements a hard and dedicated PHY for eMMC interface. Refer pin connectivity requirements when eMMC is not used
6. Include a series resistor (0Ω) on MMC0_CLK placed as close to the processor clock output pin as possible to dampen reflections. MMC0_CLK is looped back internally on read transactions, and the resistor is needed to eliminates possible signal reflections, which can cause false clock transitions. Use 0Ω initially and adjust as required to match the PCB trace impedance.
7. Required pulls for data, CMD, and clock are internally enabled by the processor eMMC hard PHY. eMMC memory provides pullup for DAT1-7 and controlled by the software (processor pullups are enabled and eMMC pullups are disabled)
8. Powering VDDS_MMC0 MMC0 PHY IO supply (1.8V) and the attached eMMC device IO supply from the same power source is required.
9. Processor eMMC hard PHY controls the clock input to the eMMC attached device
10. For implementing eMMC device reset, use a 2 input ANDing logic when the memory is used for boot. Connect RESETSTATz as one of the inputs and processor IO as another input. Add a pullup for the processor IO input near the AND gate input pin and an isolation resistor near to the processor IO output. Alternatively, use RESETSTATz as the reset source. When RESETSTATz is used as the reset source, verify the voltage level compatibility with the eMMC IO supply. Use a level shifter as required.
11. When eMMC boot is not required, the eMMC attached device reset can be controlled by the processor IO. The recommendation is to pulldown the reset of the eMMC memory device during reset
12. Add additional decoupling capacitors for attached memory device as required. Refer schematics

Schematic Review

Have you followed the below for the custom schematic design:

1. Required bulk and decoupling capacitors are provided. Compare with the SK schematics
2. Pull values for the data, command and clock signals. Compare with the SK
3. Series resistor value and placement on the clock output signal near to the processor
4. Implementation of reset logic including the IO level compatibility. Adding a capacitor at the reset input of eMMC attached device is not recommended when RESETSTATz or processor IO is connected directly to control the reset. A stand-alone reset connection to reset the eMMC memory device is not recommended
5. Supply rails connected follow the ROC
6. Quick checklist in case eMMC interface issues are observed:
   • Was the custom board designed to be compliant to the PCB trace delay requirements defined in the MMC0 timing conditions table found in the data sheet?
   • Which data transfer mode are you using when seeing the issue?
   • Have you checked to see if it works as expected when you reduce the operating speed?

Additional

1. The PHY implemented for the AM62Px MMC0 port only supports eMMC devices and does not require external pulls to hold the attached device in a known state until the port is initialized. Internal pulls are automatically turned on as soon as the processor is powered. There are no PADCONFIG registers associated with the MMC0 pins. The internal pulls associated with the MMC0 pins are controlled by the MMC0 host and PHY.
   • The MMC0_CLK pin will be driven low after reset. An external pulldown will not be required
   • The MMC0_DAT0-7 pins will have internal pullups. Turned on during reset. So, an external pullup will not be required
   • The MMC0_CMD pin will be driven high during reset. So, an external pullup will not be required
   • The MMC0_DS pin will have the internal pulldown turned on during reset. So, an external pulldown will not be required
   In summary, external pull resistors are not required on any of the MMC0 signals.
2. Verify that the eMMC_RSTn reset input is enabled in the eMMC device (eMMC non-volatile configuration space) for the reset logic to be functional. The GPIO reset option makes it possible for software to reset the attached device (eMMC or OSPI or SD card or OLDI or EPHY) without resetting the entire processor if there is a case where the peripheral becomes unresponsive. An option is to eliminate the GPIO option and only use the reset output (warm) where software forces a warm reset if the peripheral becomes unresponsive. However, using warm reset status output resets the entire device, rather than trying to recover the specific peripheral without resetting the entire device. When RESETSTATz is used to reset the attached device, verify the IO voltage level of the attached device matches the RESETSTATz IO voltage level. A level translator is recommended to match the IO voltage level. Alternatively, use a resistor divider, provided optimum impedance value of the resistor divider is selected. If too high, the rise and fall time of the eMMC reset input can be slow and introduce too much delay. If too, low it causes the processor to source too much steady-state current during normal operation
3. ANDing logic additionally performs level translation. Verify the reset IO level compatibility before optimizing the reset ANDing logic. IO level mismatch can cause supply leakage and affect processor operation