SPRAD26 April   2022 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1SPI: Serial Peripheral Interface
  3. 2J7200/J721e MCSPI Support
    1. 2.1 MCSPI Features
  4. 3SPI: Master Mode Enabling and Validation on Linux
    1. 3.1 Enable SPI Instances of J721e/TDA4VM
    2. 3.2 Enable SPIDEV on TD4VM SDK
    3. 3.3 Exercise SPI From User Space on TI J7/TDA4x Using Standard Linux spidev_test Tool
  5. 4SPI: Slave Mode Enabling and Validation on Linux
    1. 4.1 Enable SPI Instances of J7200
    2. 4.2 Enable DMA for MCSPI4 Slave Node
    3. 4.3 Enable SPIDEV and SPI_SLAVE Configs
    4. 4.4 Test SPI Slave Functionality From User Space on TI J7200 Using Standard Linux spidev_test Tool
    5. 4.5 SPI Slave Testing Using spi-slave-time
    6. 4.6 Linux SPI Slave Challenges
    7. 4.7 Linux SPI Slave Mode General Limitations
    8. 4.8 McSPI SPI Slave Mode Limitations
  6. 5References

MCSPI Features

The MCSPI modules include the following main features:

  • Serial clock with programmable frequency, polarity, and phase for each channel
  • Wide selection of MCSPI word lengths, ranging from 4 to 32 bits
  • Up to four master channels, or single channel in slave mode
  • Single interrupt line for multiple interrupt source events
  • Enable the addition of a programmable start-bit for MCSPI transfer per channel (start-bit mode)
  • Supports start-bit write command
  • Supports start-bit pause and break sequence
  • Programmable shift operations (1-32 bits)
  • Programmable timing control between chip select and external clock generation
  • Built-in FIFO available for a single channel.
  • Master multichannel mode:
    • Full duplex/half duplex
    • Transmit-only/receive-only/transmit-and-receive modes
    • Flexible input/output (I/O) port controls per channel
    • Programmable clock granularity
    • MCSPI configuration per channel. This means, clock definition, polarity enabling and word width