3 AMC1306 Bitstream and Fail-Safes

The AMC1306 device features four fail-safe conditions depending on different scenarios that could potentially impact the delta-sigma modulator and the system. These fail-safe conditions have predefined effects on the bitstream output produced and therefore can be analyzed by the MCU to detect and distinguish between the different fail-safe conditions.

Figure 3-1 shows the AMC device used requires a 5 V or 3.3 V high-side supply voltage (AVDD). When AVDD is not present, the DOUT output of the modulator remains low for the entire duration that AVDD is missing.

Once the high-side supply voltage returns to correct voltage levels, the device has two startup periods during which the output bitstream are assumed to be invalid. The first startup period is interface startup (ISTART). This interface startup lasts for 32 CLKIN cycles and consists of a test-pattern issued by the device, which consists primarily of alternating 0 and 1 bits. The second startup time is the analog startup (ASTART). This analog startup begins as soon as AVDD returns to a good voltage and lasts for approximately 0.5 ms. To simplify these conditions, it is assumed that the bitstream is invalid for a full 0.5 ms after AVDD returns to the appropriate level.

The next fail-safe occurs when the operating common-mode input voltage, VCM, exceeds the overvoltage limit, VCMov. When this occurs, DOUT will remain at a static value of 1. When VCM is brought back below the overvoltage threshold value, the output of the AMC1306 device will return to a valid bitstream.

Examining these two fail-safe conditions in parallel, the missing high-side voltage fail-safe has a higher priority compared to the common-mode overvoltage fail-safe. When both conditions are present, the delta-sigma output bitstream will be low. After AVDD is restored to the device, the 32 CLKIN-cycle interface startup pattern will have priority over the overvoltage condition. After the 32 CLKIN cycles have elapsed and the overvoltage condition is still present, the output DOUT will be high. These conditions and their priority are shown in Figure 3-3.

The remaining two fail-safe states are used to detect input-overrange conditions and distinguish these from the missing high-side and common-mode overvoltage conditions. The input voltage clipping ranges differ depending on the device being used. For the AMC1306x25 device, the clipping occurs at +- 320 mV. For a negative full-scale range input, the output bitstream will consist of a pattern of 127 0s followed by a single 1. This pattern continually repeats until the FSR condition is relieved. Depending on the level of overdrive, the single 1 may be extended to two or three 1s. With this unique configuration, it is possible to distinguish the fail-safe condition from a missing AVDD fail-safe.

A similar bitstream configuration occurs when a positive full-scale range input is applied to the device. When the input voltage exceeds the positive clipping voltage, DOUT will display a continuous pattern of 127 1s followed by a single 0 bit. Likewise, depending on the level of overdrive, the single 0 may be extended to two or three 0s.