SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

4.7.1 Hardware Setup and Connections

The following hardware is needed to run the demo:

Optional

  • Logic Analyzer (for viewing CCSI bus signals)

Setup the hardware as follows:

  1. Setup the LAUNCHXL-F280039C EVM with default settings:
    1. Populate JP1 to connect the 5 V power and GND from the USB-C connector to the XDS110 side of the board.
    2. Populate JP2 to connect the 5 V power on the XDS110 side of the board to the rest of the LaunchPad.
    3. Populate the TCK and TMS jumpers on J101 to connect the XDS110 to the F280039C device (the other jumpers on J101 can be also populated if desired).
    4. S3 boot mode set to Flash boot (optional).
  2. Setup the LP5891Q1EVM as follows:
    1. Switch S1 set to SOUTHOST to route the serial data output from the LP5891-Q1 device back to the host controller.
    2. Jumper J6 set to MCU5V to select the 5 V supply from the host controller.
    3. Jumper J7 set to "3V3 VR" to select 3.3 V power supply for VLEDR.
  3. Plug in the LP5891Q1EVM to site 1 on the LAUNCHXL-F280039C EVM. Use the 5 V, 3V3, and GND markings on both boards as a guide to correctly orient the boards.
  4. Connect a USB-C cable to the USB header on the LAUNCHXL-F280039C EVM. When the USB cable is plugged into a USB2.0/USB3.x port, the LaunchPad and LP5891Q1EVM receives power from the USB port.
  5. Proceed to the software setup.