SPRAD66B February   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Additional Information: SOC Package Delays
  8. 5Summary
  9. 6References
  10. 7Revision History

4 Additional Information: SOC Package Delays

The SOC package delays provided in this appendix are measured from SOC die pad to SOC package pin. The skew limits specified in Table 2-6 and Table 2-7 are measured from SOC die pad to DRAM package pin (including these delays inside the SOC package). The designer shall sum these package delays with the PCB delays for each net when checking for initial complance with the skew limits. Simulations of the propagation delays are then required to confirm the delays satisfy the requirements.

Processor Pin Name AM62Ax AMB Package Delay (ps) AM62Px AMH Package Delay (ps) AM62Dx ANF Package Delay (ps) Net Class Description
DDR0_A0 22.88 21.5 24 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A1 28.25 22.0 28 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A2 22.05 20.7 26 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A3 18.51 21.5 16 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A4 32.23 21.3 31 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A5 20.59 26.5 20 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A6 24.25 20.9 28 ADDR_CTRL Used with DDR4
DDR0_A7 33.50 28.4 34 ADDR_CTRL Used with DDR4
DDR0_A8 16.81 25.8 13 ADDR_CTRL Used with DDR4
DDR0_A9 25.80 26.7 27 ADDR_CTRL Used with DDR4
DDR0_A10 27.13 26.4 27 ADDR_CTRL Used with DDR4
DDR0_A11 17.62 16.9 20 ADDR_CTRL Used with DDR4
DDR0_A12 23.81 21.2 23 ADDR_CTRL Used with DDR4
DDR0_A13 27.85 24.0 26 ADDR_CTRL Used with DDR4
DDR0_ACT_N 13.90 11.4 12 ADDR_CTRL Used with DDR4
DDR0_ALERT_N 12.55 20.4 15 N/A Used with DDR4
DDR0_BA0 14.08 9.2 12 ADDR_CTRL Used with DDR4
DDR0_BA1 29.69 21.4 30 ADDR_CTRL Used with DDR4
DDR0_BG0 20.88 24.9 20 ADDR_CTRL Used with DDR4
DDR0_BG1 17.32 12.1 21 ADDR_CTRL Used with DDR4
DDR0_CAS_N 16.50 17.6 13 ADDR_CTRL Used with LPDDR4 and DDR4 (LPDDR4: copy of CS1 for LPDDR4_CS1_B)
DDR0_CK0 33.36 26.6 33 CK0 Used with LPDDR4 and DDR4
DDR0_CK0_N 31.54 25.1 31 CK0 Used with LPDDR4 and DDR4
DDR0_CKE0 23.42 24.0 23 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_CKE1 19.39 19.7 17 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_CS0_N 18.68 16.6 18 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_CS1_N 19.25 22.1 19 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_DM0 42.32 33.9 36 BYTE0 Used with LPDDR4 and DDR4
DDR0_DM1 32.47 23.8 31 BYTE1 Used with LPDDR4 and DDR4
DDR0_DM2 37.15 25.6 39 BYTE2 Used with LPDDR4 and DDR4
DDR0_DM3 34.93 39.9 42 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ0 40.49 40.1 43 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ1 40.10 37.4 35 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ2 37.54 37.2 36 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ3 38.09 37.5 35 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ4 37.74 43.1 35 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ5 39.28 37.1 35 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ6 45.09 35.3 42 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ7 46.22 32.9 42 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ8 36.45 29.1 32 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ9 27.44 31.6 24 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ10 37.16 22.2 34 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ11 35.57 29.9 32 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ12 34.30 25.2 27 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ13 29.40 22.4 27 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ14 40.85 24.8 37 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ15 42.33 32.6 43 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ16 44.73 25.8 29 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ17 37.56 22 30 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ18 36.87 22.1 29 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ19 28.07 22.2 28 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ20 35.14 32.8 44 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ21 26.37 30.2 40 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ22 29.40 25.3 36 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ23 29.78 28.4 37 BYTE2 Used with LPDDR4 and DDR4
DDR0_DQ24 42.45 37.2 45 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ25 37.11 30.6 38 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ26 34.38 33.3 41 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ27 34.47 38.7 36 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ28 35.37 34.7 36 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ29 41.43 31.5 39 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ30 37.85 36.2 35 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQ31 41.82 37.1 40 BYTE3 Used with LPDDR4 and DDR4
DDR0_DQS0 45.57 40.1 43 DQS0 Used with LPDDR4 and DDR4
DDR0_DQS0_N 47.21 41.8 44 DQS0 Used with LPDDR4 and DDR4
DDR0_DQS1 35.22 28.1 32 DQS1 Used with LPDDR4 and DDR4
DDR0_DQS1_N 37.13 29.5 34 DQS1 Used with LPDDR4 and DDR4
DDR0_DQS2 32.77 30.2 37 DQS2 Used with LPDDR4 and DDR4
DDR0_DQS2_N 34.04 31.8 38 DQS2 Used with LPDDR4 and DDR4
DDR0_DQS3 45.45 37.1 46 DQS3 Used with LPDDR4 and DDR4
DDR0_DQS3_N 43.87 35.6 45 DQS3 Used with LPDDR4 and DDR4
DDR0_ODT0 19.87 13 22 ADDR_CTRL Used with DDR4
DDR0_ODT1 24.27 21.1 23 ADDR_CTRL Used with DDR4
DDR0_PAR 29.55 28.1 27 ADDR_CTRL Used with DDR4
DDR0_RAS_N 14.99 10.3 12 ADDR_CTRL Used with LPDDR4 and DDR4 (LPDDR4: copy of CS0 for LPDDR4_CS0_B)
DDR0_RESET0_N 14.20 31.9 12 ADDR_CTRL Used with LPDDR4 and DDR4, No length matching requirement
DDR0_WE_N 11.68 20.5 13 ADDR_CTRL Used with DDR4