SPRAD66B February   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Additional Information: SOC Package Delays
  8. 5Summary
  9. 6References
  10. 7Revision History

2.13 CK0 and ADDR_CTRL Routing Specification

Skew within the CK0 and ADDR_CTRL net classes directly reduces setup and hold margin for the ADDR_CTRL nets. Thus, this skew must be controlled. The routed PCB track has a delay proportional to the length. Thus, the delay skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match skew on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and the associated clock. Consider Z-axis delays (VIAs) with accurate stackup information during analysis.

The DDR PHY includes a per-bit deskew feature, enabled by default. This capability allows signal routing with looser delay matching tolerance as specified in Table 2-6. If this feature is disabled, skews must be tightly matched. Measure the propagation delay of each signal from the SoC die to the DRAM device pin. The designer is free to length match using smaller tolerance than values shown in the table. Refer to Additional Information: SOC Package Delays during the initial PCB design phase. Perform a simulation and generate a delay report to confirm skews are within the specified tolerance.

Table 2-6 lists the limits for the individual segments that comprise the routing from the processor to the SDRAM. These segment lengths coincide with the CK0 and ADDR_CTRL topology diagram shown previously in Figure 2-6, Figure 2-7, and Figure 2-8. By controlling the routed lengths for the same segments of all signals in a routing group, the signal delay skews are controlled. Most PCB layout tools can be configured to generate reports to assist with this validation. If this cannot be generated automatically, this must be generated and verified manually.

Delay reports from PCB layout tools use a simplified calculation based on a constant propagation velocity factor. To get the design close to success prior to simulation, TI recommends initially skew matching in PCB layout tool to a target less than 20% of the limit in Table 2-6. To make sure the PCB design meets all requirements, the design is required to be simulated and those results compared with the simulation results defined in Section 3. Simulations must be power-aware and consider the entire system IO buffers, SOC package, PCB traces, memory packages, on-die decoupling circuits, and number of die.

Table 2-6 CK0 and ADDR_CTRL Routing Specifications
NumberParameterMINTYPMAXUNIT
LP4_ACRS1Propagation delay of net class CK0
(RSAC1 + RSAC2)		250 (1)ps
LP4_ACRS2Propagation delay of net class ADDR_CTRL
(RSAC3 + RSAC4, RSAC5)		250 (1)ps
LP4_ACRS3Skew within net class CK0 (Skew of DDR0_CK0 and DDR0_CK0_n )
(RSAC1 + RSAC2)		0.75 (2)(3)ps
LP4_ACRS5Skew between each T-branch signal pair
RSAC2 or RSAC4 Skew (4)		-0.100.1ps
LP4_ACRS6Skew across ADDR_CTRL and CK0 clock net class, relative to propagation delay of CK0 net class
(RSAC1 + RSAC2) - (RSAC3 + RSAC4), (RSAC1 + RSAC2 - RSAC5)(5)		-75 (3)(6)75 (3)(6)ps
LP4_ACRS7VIAs per trace4 (1)VIAs
LP4_ACRS8VIA Stub Length 20 (7)Mils
LP4_ACRS9VIA count difference0 (8)VIAs
LP4_ACRS10Center-to-center CK0 to other LPDDR4 trace spacing 5w(9)
LP4_ACRS11Center-to-center ADDR_CTRL to other LPDDR4 trace spacing 5w(9)
LP4_ACRS12Center-to-center ADDR_CTRL to self or other ADDR_CTRL trace spacing 3w(9)
LP4_ACRS13CK0 center-to-center spacing (10)See note below
LP4_ACRS14CK0 spacing to non-DDR net 5w(9)
(1) Max value is based upon conservative signal integrity approach. FR4 material assumed with Dk equals approx. 3.7 - 3.9 and Df equals approx. 0.002. This value can be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) Recommendation for PCB layout tool design. Required to be verified by simulation(11), confirm JEDEC defined Vix_DQS_ratio (20%) and Vix_CK_ratio (25%) are satisfied, also need to have good eye margins - refer to Section 3.5.3.1.
(3) Consider the delays from SOC die pad to the DRAM pin (that is, delays of SOC package and delays of PCB upto the DRAM pin. DRAM package delays are omitted). Consider one leg of any T-branch trace segments when delay matching. Refer to Additional Information: SOC Package Delays.
(4) Recommended skew control on T-branch trace segments (Balanced-T) is intended to optimize signal integrity (waveform reflections). This is not required nor recommended to match skew across all T-branch trace segments, just for each branch of a specific signal.
(5) Recommend routing net classes CK0 and ADDR_CTRL on same signal layer for better skew control.
(6) Simulation(11) must be performed and the delay report analyzed to make sure skew is within the limit. Delay reports from PCB layout tools use a simplified calculation based on a constant propagation velocity factor. TI recommends initially skew matching in PCB layout tool to a target less than 20% of the limit.
(7) VIA stub control (micro VIA or backdrilling) can be required if operating LPDDR4 above 3200Mbps depending on simulation(11) results.
(8) VIA count difference can increase by 1 only if accurate 3-D modeling of the signal flight times; including accurately modeled signal propagation through VIAs and has been applied to make sure skew maximums are not exceeded.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints). Spacing minimums can be relaxed if simulations(11) accurately capture crosstalk between neighboring victim and aggressor traces and show good margin. Consider also VIA spacing. Signals with adjacent VIAs near SOC must not also have adjacent VIAs near the DRAM.
(10) P to N spacing set to make sure of proper differential impedance. The designer must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing must be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer. Refer to impedance targets in Table 1-1.
(11) Simulation refers to a power-aware IBIS Signal Integrity (SI) simulation. Simulate across process, voltage, and temperature (PVT). Refer to Section 3.