SPRAD66B February   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Additional Information: SOC Package Delays
  8. 5Summary
  9. 6References
  10. 7Revision History

2.14 Data Group Routing Specification

Skew within the Byte signal net class directly reduces the setup and hold margin for the DQ and DM nets. As described with the ADDR_CTRL signal net class and associated CK0 clock net class, this skew must be controlled. The data byte skew must be managed through controlling the lengths of the routed tracks within a defined group of signals. The only way to practically match skews on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and the associated clock. Consider Z-axis delays (VIAs) with accurate stackup information during analysis.

The DDR PHY includes a per-bit deskew feature, enabled by default. This capability allows signal routing with looser delay matching tolerance as specified in Table 2-7. If this feature is disabled, then skews must be tightly matched. Measure the propagation delay of each signal from the SoC die to the DRAM device pin. The designer is free to length match using smaller tolerance than values shown in the table. Refer to Additional Information: SOC Package Delays during the initial PCB design phase. Perform a simulation and generate a delay report to confirm skews are within the specified tolerance.

Note: This is not required nor recommended to match the lengths across all byte lanes. Length matching is only required within each byte.

Table 2-7 contains the routing specifications for the Byte0, Byte1, Byte2, and Byte3 routing groups. Each signal net class and the associated clock net class is routed and matched independently. These parameters are recommendations only, intended to get the design close to success prior to simulation. To make sure the PCB design meets all requirements, the design is required to be simulated and those results compared with the simulation results defined in Section 3.

Table 2-7 Data Group Routing Specifications
Number Parameter MIN TYP MAX UNIT
LP4_DRS1 Propagation delay of net class DQSx
(RSD1) 		250 (1) ps
LP4_DRS2 Propagation delay of net class BYTEx
(RSD2)		 250 (1) ps
LP4_DRS3 Difference in propagation delays of CK0 pair and each DQS pair. (RSAC1 + RSAC2 - RSD1)(2) 0 (3)(4) 3(3)(4) tCK
LP4_DRS4 Skew within net class DQSx
Skew of DQSx to DQSx_n (RSD1) 		1.5 (4)(5) ps
LP4_DRS5 Skew across DQSx and BYTEx net classes.
(Skew of RSD1 and RSD2) (6)		 150 (3)(4) ps
LP4_DRS6 Difference in propagation delays of shortest DQ/DM bit in BYTEx and respective DQSx.
(RSD2 - RSD1)		 -50 (3)(4) ps
LP4_DRS7 VIAs Per Trace 2 (1) VIAs
LP4_DRS8 VIA Stub Length 40 (7) Mils
LP4_DRS9 VIA Count Difference 0 (8) VIAs
LP4_DRS10 RSD1 center-to-center spacing (between clock net class) 5w (9)
LP4_DRS11 RSD1 center-to-center spacing (within clock net class) (10) See note below
LP4_DRS12 RSD2 center-to-center spacing (between signal net class) 5w (9)
LP4_DRS13 RSD2 center-to-center spacing (to self or within signal net class) 3w (9)
(1) Max value is based upon conservative signal integrity approach. FR4 material assumed with Dk equals approx. 3.7 - 3.9 and Df equals approx. 0.002. This value can be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) Propagation delay of CK0 pair must be greater than propagation delay of each DQS pair. Consider one leg of any T-branch trace segments when delay matching.
(3) Simulation(11) must be performed and the delay report analyzed to make sure delays are within the limit. Delay reports from PCB layout tools use a simplified calculation based on a constant propagation velocity factor. TI recommends initially delay matching in PCB layout tool to a target less than 20% of the limit.
(4) Consider the delays from SOC die pad to the DRAM pin (that is, delays of SOC package and delays of PCB up to the DRAM pin. DRAM package delays are omitted). Refer to Additional Information: SOC Package Delays.
(5) Recommendation for PCB layout tool design. Required to be verified by simulation(11), confirm JEDEC defined Vix_DQS_ratio (20%) and Vix_CK_ratio (25%) are satisfied, also need to have good eye margins. Refer to Section 3.5.3.1.
(6) Skew matching is only done within a byte including DQS. Skew matching across bytes is neither required nor recommended.
(1) Recommended skew control on T-branch trace segments (Balanced-T) is intended to optimize signal integrity (waveform reflections). This is not required nor recommended to match skew across all T-branch trace segments, just for each branch of a specific signal.
(1) Recommendation for PCB layout tool design. Required to be verified in simulation(11). Simulating worst PVT corner, verify a required minimum of CK - 75ps and maximum of CK + 75ps is satisfied. Recommend routing net classes CK0 and ADDR_CTRL on same signal layer for better skew control.
(7) VIA stub control (micro VIA or backdrilling) is required if operating LPDDR4 above 3200Mbps depending on simulation(11) results.
(8) VIA count difference can increase by 1 only if accurate 3-D modeling of the signal flight times; including accurately modeled signal propagation through VIAs and has been applied to make sure skew maximums are not exceeded.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints). Spacing minimums can be relaxed if simulations(11) accurately capture crosstalk between neighboring victim and aggressor traces and show good margin. Consider also VIA spacing. Signals with adjacent VIAs near SOC must not also have adjacent VIAs near the DRAM.
(10) P to N spacing set to make sure proper differential impedance. The designer must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing must be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer. Refer to impedance targets in Table 1-1.
(11) Simulation refers to a power-aware IBIS Signal Integrity (SI) simulation. Simulate across process, voltage, and temperature (PVT). Refer to Section 3.