SPRAD72 February 2023 F29H850TU , F29H859TU-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The Ethernet physical layer (PHY) is a transceiver component for transmitting and receiving data of Ethernet frames and the PHY device implements the physical layer in the open systems interconnection (OSI) model. The PHY device acts as a bridge between the medium access controller (MAC - data link layer in OSI model) and a physical medium such as copper or fiber cable.
The serial management interface (SMI) provides access to the PHY device internal register space for status information and configuration. Proper PHY configuration using SMI is fundamental during the prototype stage, and also crucial to meeting the requirements of the lowest deterministic latency and fastest link detection in industrial Ethernet applications such as EtherCAT®. The SMI is compatible with IEEE 802.3 clause 22 and clause 45. The implemented register set consists of the registers required by the IEEE 802.3 plus several others to provide additional visibility and controllability of the PHY device.
This application note provides guidance on the Ethernet PHY configuration using SMI of the EtherCAT slave controller (ESC) in the C2000™ device for industrial applications.
C2000™ and Code Composer Studio™ are trademarks of Texas Instruments.
EtherCAT® and Beckhoff® are registered trademarks of Beckhoff Automation GmbH.
All trademarks are the property of their respective owners.
Ethernet for Control Automation Technology (EtherCAT®) is an Ethernet-based fieldbus system, invented by Beckhoff® Automation and is standardized in IEC 61158. All the slave nodes connected to the bus interpret, process, and modify the addressed data on the fly (when needed basis), without having to buffer the frame inside the node. This real-time behavior, frame processing, and forwarding requirements are implemented by the EtherCAT slave controller hardware. EtherCAT does not require software interaction for data transmission inside the slaves. EtherCAT only defines the MAC layer while the higher layer protocols and stack are implemented in software on the microcontrollers connected to the ESC. The SMI in C2000 ESC is called PHY management interface used for communication with the Ethernet PHYs. See #GUID-E7718E96-EBB4-439E-B6C0-5E8B5C66323F for the connectivity of SMI.
MDIO must have a pullup resistor (4.7 kΩ recommended) externally. MCLK is driven rail-to-rail, idle value is HIGH.
The SMI includes the management clock (MDC) and the management input/output data pin (MDIO). MDC is sourced by the ESC, and can run at a maximum clock rate of 25 MHz. MDC is not expected to be continuous, and can be turned off by the ESC when the bus is idle.
MDIO is sourced by the ESC and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC. MDIO pin requires a pullup resistor, which pulls MDIO high during IDLE and turnaround.
When selecting the proper PHY for EtherCAT, first review the Application note – PHY selection guide on the EtherCAT home page. This application note describes the specifications and the recommendations of PHY performance from the EtherCAT perspective. The document also lists a variety of PHYs from TI, such as the DP836x, DP838x, TLK10x, and TLK11x.
Proper configuration of PHY to comply with IEEE 802.3 100BaseTX or 100BaseFX, includes:
To setup the PHY in the correct mode to work in the EtherCAT environment, the serial management interface (SMI) can be used to program the PHY to be setup in a specific mode.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, an x-bit address is used. During power up or hardware reset, the PHY device latches the PHY_AD[x:0] configuration pins to determine the address. The address can be changed by adding the required pullup or pulldown resistors defined in the bootstrap section of the PHY device data sheet. The bootstrap pin can also be used for PHY configuration. This application note only focuses on using the SMI. See #GUID-27DBB9E2-FB45-4939-A0E3-826F03E4C20E for the hardware bootstrap diagram.
The C2000 ESC addresses the Ethernet PHYs typically using the logical port number plus the PHY address offset. In the best situation, the Ethernet PHY addresses correspond with the logical port number, so PHY addresses 0 and 1 are used. A PHY address offset of 0 to 31 can be applied which moves the PHY addresses to any consecutive address range. The ESC module expects logical port 0 to have PHY address 0 plus the PHY address offset. The PHY address offset can be selected in register ESCSS_MISC_CONFIG.PHY_ADDR[4:0].
Before entering into the desired operation mode, the PHY device must get out of the RESET condition by applying a high level to the RESET pin. This RESET signal is generated out of the ESC module. Since there are no pull devices active on the MCU during and after reset, a pulldown resistor must be added on this signal on the board level. In some cases, PHYs can be released from reset after releasing the ESC module. To generate a delay, the pin for nPHY_RESET can be used as an I/O and is switched later to the alternate output function. Moreover, a hardware reset can reinitialize all the PHY registers to default values by applying a low pulse, with a duration of at least 10 μs (T1) to the RESET pin (take DP83822 PHY for example, see #GUID-84B7F4FA-0AA0-418D-90DE-9F29ED8BE5C3).
The interface diagram between ESC and PHY device is shown in #GUID-3E254514-88D8-4C00-BC6A-F7003CED3FD2. The PHY can be clocked using the ESCSS_PHY_CLK signal, if needed, otherwise provide an external 25-MHz source to the PHY and ESC (both must be clocked from the same source).