A basic totem-pole PFC structure is shown in Figure 1-1. Different from the boost converter, the control of a totem-pole PFC is much more complex. Based on the input voltage VAC polarity, high frequency FETs Q1 and Q2 alternately work as a PFC active switch or sync switch, while slow frequency FETs Q3 and Q3 switch at grid frequency. The basic control logic could refer to Control challenges in a totem-pole PFC. In the actual applications, it is required to consider how to better handle the transient conditions, when the power stage enters overload conditions, light load or fault conditions, which is discussed in the proposed PWM configurations.

When PFC runs into overload conditions, for example, during AC voltage transient from high line to low line, or some fault events occur, it is required to implement overcurrent protection with CBC based PWM shut down control, in order to limit the PFC inductor current instead of shutting down the power stage. Normally, it is common to configure both PWM output for Q1 and Q2 to turn off together as soon as the inductor current reaches the overcurrent threshold. However, it might induce the risk for the power stage, especially during high temperature.

Because of the reverse recovery issue, a regular MOSFET cannot be used in a continuous-conduction mode (CCM) totem-pole PFC, so Q1 and Q2 need to be GaN or SiC FETs. As discussed in the third quadrant operation of GaN, located in Does GaN Have a Body Diode? - Understanding the Third Quadrant Operation of GaN, the reverse conduction voltage Vsd is much higher under third quadrant operation, ranging from 3 V~5 V, or even more with larger reverse current, which also applies for SiC. The high reverse conduction voltage can cause excessive losses, and it brings concerns on device’s thermal limitation and system reliability. Take positive cycle operation as example, showed in Figure 1-2, with the traditional PWM configurations, after both high side and low side FETs shut down at overcurrent event, large inductor current will continue to flow on the high side FET, so the conduction loss increases due to the third quadrant operation, which might cause the junction temperature rise up and lead to thermal damage for the GaN or SiC.

Therefore, an ideal CBC protection scheme for the PWM configurations is shown in Figure 1-3. The PWM for the sync switch (high side FET Q1 for positive cycle in this case) should be turned on after the active switch turns off, with a customized dead time. However, the traditional trip-zone (TZ) submodule of ePWM could not be used to achieve the above logic. As shown in Figure 1-4, when a cycle-by-cycle trip event occurs, the action specified in the TZ submodule is carried out immediately on the ePWMxA and ePWMxB outputs, without any delay, since the TZ submodule is the last part before the ePWM outputs. In addition, for totem pole PFC, the ePWM output used for active FET and sync FET is different based on the VAC polarity, so the actions set inside the TZ submodule could not work for both positive and negative cycle automatically.