SPRADD9 September 2023 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
When the power rating increased, interleaved topologies are common to selected, for better thermal design and ripple current performance. Therefore, 2 phase interleaved totem pole PFC is also popular in high power applications. In Leverage New Type ePWM Features for Multiple Phase Control, it showed flexibility of the phase register TBPHS when configuring the phase shift relationship among different ePWM modules, but since TBPHS does not provide the shadow mode, cares should be taken when the switching frequency changes with a large step. For CCM mode totem pole PFC, it uses fixed frequency normally, it is fine to enable the phase register for 2 phase interleaved configurations. In this document, another more simplified scheme is discussed, which is helpful to implement the frequency dithering feature for the EMI optimization.
As shown in Figure 5-1, ePWM1 and ePWM2 are used as the example, representing the control modules for the master phase and the slave phase, respectively. Instead of using the phase shift register, both ePWM modules share the same time base. Different from the PWM configurations in Section 1, up-down count mode is used, and the duty cycle for the active FET is centralized with the Period event for the master phase (Phase 1), while it is centralized with the ZERO event for the slave phase (Phase 2). With such design, the 180° phase shift is achieved naturally. Another benefit is that, if the switching frequency is required to change, for example, for the frequency dithering function, the register linking scheme with the EPWMXLINK register can ensure the period registers of different ePWM modules are written simultaneously.