4 Control Law Accelerator

Many complex real-time control applications require an even higher level of processing performance from an integrated control-law accelerator. For example, a typical power digital controller consists of an analog-to-digital converter (ADC) to capture the input data, a math engine to compute the control law algorithms (for example, PID, two-pole or two-zero, and three-pole or three-zero compensators), and a PWM channel to output the calculated waveform. A high-performance MCU integrates these functions within a single device to minimize latency (and reduce system complexity and cost), yielding the absolute minimum sample to output delay.

Support for 32-bit floating-point math-intensive computations is standard, so low-level control loops can be managed with more performance and efficiency than the CPU. Additionally, direct access to memory and control peripherals, such as the A/D convertor and PWM modules, further helps to minimize latency. An integrated control law accelerator of this kind can respond to peripheral triggers without CPU intervention. The accelerator does not use interrupts for hardware synchronization, nor must the accelerator do any context switch, increasing efficiency. This approach eliminates jitter and the execution time becomes deterministic. For detailed benchmarks and insights on these accelerators, see the Enhancing the Computational Performance of the C2000^™ Microcontroller Family application note.