2 OptiFlash Detailed Overview

OptiFlash consists of TI patented hardware and software enhancements that can accelerate boot from on-PCB flash and enable secure (ISO 21434) and high integrity (ISO 26262, IEC 61508) compliant data transfers. OptiFlash allows TI MCUs to improve the Flash:SRAM ratio to anywhere between 8:1 and 4:1. OptiFlash can also provide the flexibility of addressing up to 128MB of external on-PCB flash. A detailed overview of the various accelerators that are a part of OptiFlash shown in Figure 1-2.

Boot/Overlay Accelerator: comprises of fast local copy (FLC), a dedicated DMA engine, capable of reading-while-writing to download code (from external flash) while allowing CPU execution in parallel. “Up to 2MB sized boot images can be downloaded in approximately 9 mS (milliseconds). System initialization time will depend on the application. From Software side, application layout in memory based on call graph is done to optimally leverage the pre-fetch hardware.

Remote L2 (RL2) Cache: comprises of customized caches for on-PCB flash for read-only data/code that can reduce flash read access time by as much as ~ 90%.

Smart Placement: Provides tools to implement profiling-based application optimization and uses TI Arm CLANG Compiler enhancement to profile applications software and identify deadline critical software code to place either in TCM or OCSRAM for an up to approximately 20% - 40% performance boost.

The above image shows impact of smart placement on other variables. All of this is possible because of compiler enhancement and new tools which are part of smart placement.

OptiShare: Tools to automatically identify common code across cores which leverages hardware feature of Region Address Translator (RAT) to reduce code size by placing shared core/read-only-data single time in the memory.

XIP (eXecute-in-place) Safety: Implements on-the-fly (in-line) hardware single error correct, dual error detect (SECDED) Error Correction Code (ECC) to improve data integrity for Functional Safety Compliant Applications. Includes four syndromes per 32-byte chunk, ECC in address and MAC and a safety compliant time-out-gasket (TOG) that interrupts the CPU if the on-PCB flash is ‘hung’ for some reason.

XIP Security: implements on-the-fly hardware decryption and authentication for Cyber Security (for example, ISO 21434) compliance. Includes (per client) firewall to prevent un-intended access from an un-authorized host.

Firmware-over-the-air (FOTA) Updates: hardware acceleration for XIP + simultaneous WRITE which could enable 10x – 80x reduction in XIP down-time while performing RWW.