SPRADH0 August   2024 AM625 , AM6442 , AM69 , TDA4VM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 What is EtherCAT?
    2. 1.2 What is a PLC?
    3. 1.3 What is CODESYS?
  5. 2Evaluation Platform and Methods
    1. 2.1 Hardware
    2. 2.2 Software
    3. 2.3 Test Topology
  6. 3Performance Metrics
    1. 3.1 Cyclictest Performance Metrics
    2. 3.2 EtherCAT Performance Metrics
  7. 4Optimizations
    1. 4.1 Implemented Optimizations
    2. 4.2 Future Considerations
      1. 4.2.1 Set Maximum CPU Frequency
      2. 4.2.2 Isolate Cores
      3. 4.2.3 Set CPU Affinity
      4. 4.2.4 Isolate Cores and Set CPU Affinity
      5. 4.2.5 Ksoftirqs to FIFO
      6. 4.2.6 Increase the Real-Time Scheduling Time
      7. 4.2.7 Disable irqbalance
      8. 4.2.8 Use Separate Network Interface Card (NIC)
      9. 4.2.9 Disable Unnecessary Drivers
  8. 5Summary
  9. 6References
  10. 7Appendix A: How to Setup TI Embedded Processors as EtherCAT Controller Using the CODESYS Stack
    1. 7.1 Hardware Requirements
    2. 7.2 Software Requirements
    3. 7.3 Hardware Setup
    4. 7.4 Software Setup
      1. 7.4.1 Windows PC Setup
      2. 7.4.2 EtherCAT Controller Setup
      3. 7.4.3 CODESYS Development System Project
      4. 7.4.4 Execution
    5. 7.5 How to View Performance Measurements
      1. 7.5.1 Appendix A Resources
  11. 8Appendix B: How to Enable Unlimited Runtime on CODESYS Stack
    1. 8.1 CODESYS Licensing Background
    2. 8.2 Obtaining a CODESYS License
    3. 8.3 Activating CODESYS License
      1. 8.3.1 Background
      2. 8.3.2 Recommended Steps
    4. 8.4 Verifying CODESYS License Applied
      1. 8.4.1 Known Issues With Verifying CODESYS License Applied

4.2.7 Disable irqbalance

While benchmarking on AM64x, irqbalance is observed on the list of top 10 CPU load heavy threads. Additionally, this feature automatically distributes load, generated by different interrupt sources across CPUs to achieve better system performance. This, however, can distribute load onto the same cores the EtherCAT task and other IEC tasks are running which in turn can negatively affect observed cycle time and jitter of the EtherCAT task.