SPRADI9 June 2024 AM623 , AM625
TI’s design for reliability analysis on AM62x ARM based processors family has so far consistently indicated Electro-migration as the lifetime-limiting failure mechanism. As explained previously, TI does not believe lifetime Electro-migration reliability can be adequately assessed with HTOL testing within reasonable test durations. Furthermore, as an important additional enhancement of the PDK, TI’s EDA tool flow for the Sitara AM6* product lines has the capability of integrating and reporting total FIT/Fail Fraction (FF) at our design reference conditions (105°C die junction temperature at 100k POH lifetime). As of early 2024, a software application has been developed outside of the EDA tool flow to accurately scale individual (constituent) metal or via component FF contributions to other specific single temperatures or temperature profiles. These contributions are then tallied across the SoC. Scaling is more complex than a single acceleration factor calculation because simulations show variation in the average current densities relative to the EM design-rule limits. In effect, this means each component has an individual acceleration factor (generally following Black’s Law, as explained in Appendix B).
Figure 5-1, Figure 5-2, and Figure 5-3 show POH vs. Temperature plots for AM62X product niche. In Figure 5-1 and Figure 5-2, core voltage is varied from 0.75V to 0.85V (at fixed frequency per data manual). For readability this is broken into two figures. Observe that the POH capability is roughly 25% expanded at 1% fail fraction tolerance vs. a 0.01% fail fraction, largely independent of temperature. For reference, 0.1% fail fraction at 100k POH is equivalent to 10 FIT. Figure 5-3 illustrates the effect of varying fail fraction targets at fixed voltage (and frequency) in the range of 105°C to 125°C junction temperatures. With a baseline of F=0.001 (0.1%), a relaxation to 1% failure tolerance results in roughly 18% increase in POH both at 105°C and 125°C.
All temperatures are expressed as (die) junction, consistent with TI data sheets. Reliability estimates for die-based mechanisms are all performed based on junction temperature. System-level thermal engineering by the user, comprehending package, power dissipation, system board construction and other components on the system board, is therefore critical to managing junction temperature, and, in turn, lifetime reliability.