Importantly, at the IP and SoC release stages, Electromigration (EM) and Gate Oxide Integrity (GOI) / Time-Dependent Dielectric Breakdown (TDDB) tools TI uses on the most current CMOS technologies (including for AM6*) are FIT-capable through the use of advanced Electronic Design Automation (EDA) tools. This means that FIT (Failures in Time, an expression of failure rate) is reported relative to a “design closure” condition (normally 105°C at 100kPOH, at the specified voltage and frequency conditions published in the product data manual). Furthermore, the EM flow is capable of reporting key by-individual-component average current densities (i.e. for all interconnects and vias) from simulations, enabling accurate quantitative scaling of EM reliability to customer mission profiles or alternative temperature conditions to fixed design closure conditions, an important feature discussed later. In the case of Hard IP (synthesized with physical design layout fixed), the IP are evaluated for FIT as standalone entities. The FIT contributions of Soft IP (re-synthesizable, physical layout not fixed), top-level logic (outside IP boundaries) and memories are summed for the SoC and then combined with the Hard IP (with use at SoC level limited to the bounding operating design conditions of the IP), resulting in total FIT. These FIT values are tallied separately for EM and GOI. The effects of aging on transistor components, by contrast, is generally not associated with FIT calculations, rather the design flow defines and enforces safe operating conditions and margin requirements such that effectively the failure rate within specified mission profile conditions is negligible.