SPRADI9 June   2024 AM623 , AM625

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design-Based Approach
  6. 3Background
    1. 3.1 Process Delivery Kit (PDK)
    2. 3.2 SPICE Models for Circuit Behavior
    3. 3.3 Electronic Design Automation (EDA) Tools
    4. 3.4 Package Reliability
  7. 4Comparison of Design-Based Approach vs. HTOL Approach
  8. 5AM625/623 Lifetime Reliability Analysis Results
  9. 6Conclusion
  10. 7Revision History
  11.   A Appendix – The HTOL-Based Approach
  12.   B Appendix – The Mathematic Basis for EM Reliability Estimates

Package Reliability

Package reliability is partially comprehended within the product design flow through a co-design process, coupled with die (silicon) design. Key considerations are noise minimization and signal and power integrity, as well as thermal effects. In coordination with silicon design, design rules are devised and enforced for the package to holistically affect complete product performance targets. However, package reliability is also dependent on selection of robust materials and manufacturing flows.

Extensive efforts are undertaken during package technology development to identify corner cases of process variation and the effects on manufacturability and reliability. Process limits are then set accordingly and monitoring of process capability on key parameters is performed in production, normally with Statistical Process Control (SPC). With the exception of die Bump Electromigration reliability for Flip-Chip packages, most package long-term reliability failure mechanisms encompassed by thermo-mechanical stress or oxidation/corrosion reactions. These risks are evaluated during product qualification within defined JEDEC/AEC-Q100 test conditions, but sample sizes are necessarily limited, thus limiting the capabilities of quantitative failure rate assessments. (This issue also applies to HTOL.)

Process development stage activity to build-in margin, as well as robust statistical monitoring through Manufacturing Control Plans in production are both key. However, the solder joint thermo-mechanical reliability for BGAs and bumps can be assessed quantitatively. Board Level Reliability (BLR) Temperature Cycle (T/C) Testing is performed within scope of product qualification (although can be qualified by similarity for any particular product). The BLR stress is generally continued to at least 60-70% of samples failing, enabling a generation of Weibull plots, quantifying reliability performance. (De-rating of BLR stress test conditions to application temperature cycling conditions can be needed. As the application cycling conditions can vary widely, this is typically done on a case-by-case basis.)