SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
For more details about features and additional description information on the device (LP)DDR4 Memory Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-41 and Figure 7-34 present switching characteristics for DDRSS.
NO. | PARAMETER | DDR TYPE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(DDR_CKP/DDR_CKN) | Cycle time, DDR_CKP and DDR_CKN | LPDDR4 | 1.25(1) | 20 | ns |
DDR4 | 1.25(1) | 1.6 | ns |
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.