SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
Tables and figures provided in this section define timing conditions, timing requirements and switching characteristics for clock signals.
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
INPUT CONDITIONS | |||||
SRI | Input slew rate | 0.5 | V/ns | ||
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | 5 ns ≤ tc < 8 ns | 5 | pF | |
8 ns ≤ tc < 20 ns | 10 | pF | |||
20 ns ≤ tc | 30 | pF |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
CLK1 | tc(EXT_REFCLK1) | Cycle time minimum, EXT_REFCLK1 | 10 | ns | |
CLK2 | tw(EXT_REFCLK1H) | Pulse Duration, EXT_REFCLK1 high | E*0.45(1) | E*0.55(1) | ns |
CLK3 | tw(EXT_REFCLK1L) | Pulse Duration, EXT_REFCLK1 low | E*0.45(1) | E*0.55(1) | ns |
CLK1 | tc(MCU_EXT_REFCLK0) | Cycle time minimum, MCU_EXT_REFCLK0 | 10 | ns | |
CLK2 | tw(MCU_EXT_REFCLK0H) | Pulse Duration, MCU_EXT_REFCLK0 high | F*0.45(2) | F*0.55(2) | ns |
CLK3 | tw(MCU_EXT_REFCLK0L) | Pulse Duration, MCU_EXT_REFCLK0 low | F*0.45(2) | F*0.55(2) | ns |
CLK1 | tc(AUDIO_EXT_REFCLK0) | Cycle time minimum, AUDIO_EXT_REFCLK0 | 20 | ns | |
CLK2 | tw(AUDIO_EXT_REFCLK0H) | Pulse Duration, AUDIO_EXT_REFCLK0 high | G*0.45(3) | G*0.55(3) | ns |
CLK3 | tw(AUDIO_EXT_REFCLK0L) | Pulse Duration, AUDIO_EXT_REFCLK0 low | G*0.45(3) | G*0.55(3) | ns |
CLK1 | tc(AUDIO_EXT_REFCLK1) | Cycle time minimum, AUDIO_EXT_REFCLK1 | 20 | ns | |
CLK2 | tw(AUDIO_EXT_REFCLK1H) | Pulse Duration, AUDIO_EXT_REFCLK1 high | H*0.45(4) | H*0.55(4) | ns |
CLK3 | tw(AUDIO_EXT_REFCLK1L) | Pulse Duration, AUDIO_EXT_REFCLK1 low | H*0.45(4) | H*0.55(4) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
CLK4 | tc(SYSCLKOUT0) | Cycle time minimum,SYSCLKOUT0 | 8 | ns | |
CLK5 | tw(SYSCLKOUT0H) | Pulse Duration, SYSCLKOUT0 high | A*0.4(1) | A*0.6(1) | ns |
CLK6 | tw(SYSCLKOUT0L) | Pulse Duration, SYSCLKOUT0 low | A*0.4(1) | A*0.6(1) | ns |
CLK4 | tc(OBSCLK0) | Cycle time minimum, OBSCLK0 | 5 | ns | |
CLK5 | tw(OBSCLK0H) | Pulse Duration, OBSCLK0 high | B*0.45(2) | B*0.55(2) | ns |
CLK6 | tw(OBSCLK0L) | Pulse Duration, OBSCLK0 low | B*0.45(2) | B*0.55(2) | ns |
CLK4 | tc(CLKOUT0) | Cycle time minimum, CLKOUT0 | 20 | ns | |
CLK5 | tw(CLKOUT0H) | Pulse Duration, CLKOUT0 high | C*0.4(3) | C*0.6(3) | ns |
CLK6 | tw(CLKOUT0L) | Pulse Duration, CLKOUT0 low | C*0.4(3) | C*0.6(3) | ns |
CLK4 | tc(MCU_SYSCLKOUT0) | Cycle time minimum, MCU_SYSCLKOUT0 | 10 | ns | |
CLK5 | tw(MCU_SYSCLKOUT0H) | Pulse Duration, MCU_SYSCLKOUT0 high | E*0.4(4) | E*0.6(4) | ns |
CLK6 | tw(MCU_SYSCLKOUT0L) | Pulse Duration, MCU_SYSCLKOUT0 low | E*0.4(4) | E*0.6(4) | ns |
CLK4 | tc(MCU_OBSCLK0) | Cycle time minimum, MCU_OBSCLK0 | 5 | ns | |
CLK5 | tw(MCU_OBSCLK0H) | Pulse Duration, MCU_OBSCLK0 high | D*0.45(5) | D*0.55(5) | ns |
CLK6 | tw(MCU_OBSCLK0L) | Pulse Duration, MCU_OBSCLK0 low | D*0.45(5) | D*0.55(5) | ns |
CLK4 | tc(WKUP_CLKOUT0) | Cycle time minimum, WKUP_CLKOUT0 | 5 | ns | |
CLK5 | tw(WKUP_CLKOUT0H) | Pulse Duration, WKUP_CLKOUT0 high | W*0.4(6) | W*0.6(6) | ns |
CLK6 | tw(WKUP_CLKOUT0L) | Pulse Duration, WKUP_CLKOUT0 low | W*0.4(6) | W*0.6(6) | ns |
CLK4 | tc(AUDIO_EXT_REFCLK0 ) | Cycle time minimum,
AUDIO_EXT_REFCLK0 (McASP Clock Source) |
20 | ns | |
Cycle time minimum,
AUDIO_EXT_REFCLK0 (PLL Clock Source) |
10 | ns | |||
CLK5 | tw(AUDIO_EXT_REFCLK0 H) | Pulse Duration, AUDIO_EXT_REFCLK0 high | G*0.4(7) | G*0.6(7) | ns |
CLK6 | tw(AUDIO_EXT_REFCLK0 L) | Pulse Duration, AUDIO_EXT_REFCLK0 low | G*0.4(7) | G*0.6(7) | ns |
CLK4 | tc(AUDIO_EXT_REFCLK1 ) | Cycle time minimum,
AUDIO_EXT_REFCLK1 (McASP Clock Source) |
20 | ns | |
Cycle time minimum,
AUDIO_EXT_REFCLK1 (PLL Clock Source) |
10 | ns | |||
CLK5 | tw(AUDIO_EXT_REFCLK1 H) | Pulse Duration, AUDIO_EXT_REFCLK1 high | J*0.4(8) | J*0.6(8) | ns |
CLK6 | tw(AUDIO_EXT_REFCLK1 L) | Pulse Duration, AUDIO_EXT_REFCLK1 low | J*0.4(8) | J*0.6(8) | ns |